Research And Design Of Key Technologies Of High Speed And Low Power Pipelined SAR ADC

The rapid development of the digital information age has brought us unprecedented convenience,but also new challenges.Analog-to-digital converter(ADC)plays a crucial role in connecting the analog world and the digital world.ADC is widely used in digital imaging,automatic control,wireless communication,data acquisition,instrumentation,medical equipment,etc.Especially with the explosive development of mobile communication technology,people have put forward higher requirements for the speed and accuracy of ADC.Typical high-speed ADC such as Flash ADC and Pipelined ADC usually increase sampling rate at the expense of power consumption.To improve energy efficiency,Pipelined successive approximation register analog-to-digital converter(Pipelined SAR ADC)has been proposed recently.Pipelined SAR ADC combines the high-speed advantages of Pipelined ADC and the low-power advantages consumption and a small area of successive approximation register ADC,it can achieve high energy efficiency at a high sampling rate hence it has become a research hotspot in recent years.Therefore,it is of great significance and value to study high-speed and low-power Pipelined SAR ADC.The theory,key technologies,and system structure of high-speed and low-power Pipelined SAR ADC are analyzed and studied in this thesis.We mainly focus on the residue amplifier due to it is the critical block of the whole ADC,besides,a fully dynamic high-linearity amplifier has been proposed to ensure the whole linearity of ADC while consuming less power.Additionally,to further improve the overall speed of ADC,by reducing the loop delay of SAR ADC,a high-speed parallel asynchronous successive approximation logic has been proposed,compared to the conventional logic,the proposed logic can achieve faster speed and lower power consumption.Lastly,a two-step 12bit500MS/s Pipelined SAR ADC has been designed in a 40 nm CMOS process with a power supply voltage of 1.1V,when the sinusoidal input with the frequency of 171.143 MHz,the simulation results show that the ENOB is 10.61 bit,SFDR is 72.84 d B,the power consumption of the ADC core is only 5.15 m W and the Fo M is 6.6f J/conversion-step.