Research On Analog-to-Digital Converter Based On Pipelined-SAR Hybrid Structure

With the development of 5G mobile communication system technology,the demand for high-speed and high-precision analog-to-digital converters is increasing.Pipelined ADC has many advantages in speed and precision,but has many problems such as large chip area and high power consumption.Although the SAR ADC has the characteristics of low power consumption and small chip area,it is limited in speed and accuracy due to its own structure.Pipelined-SAR ADC is a novel hybrid architecture combining the advantages of Pipelined ADC and SAR ADC.In this thesis,a Pipeline-SAR ADC with a sampling rate of 160 MS/s is designed based on TSMC 40 nm CMOS process.The main work of the thesis includes:1.Complete the system scheme design.A two-stage（6+7）SAR ADC architecture is proposed by analyzing the effects of number of sublevel and sublevel precision on the overall circuit linearity and power consumption,in which the highest bit of the second-stage SAR ADC is set as the redundant bit.The performance of Pipelined-SAR ADC is verified by MATLAB modeling and the influence of non-ideal errors on the performance of Pipelined-SAR ADC is discussed.The first stage of the whole circuit adopts V_cm-based switching timing sequence to provide stable common-mode voltage for the last stage.In the second stage,switching timing sequence based on set an down is adopted to reduce switching energy consumption.2.Complete the design of circuit speed increase.A high speed and high precision dynamic comparator is proposed for high speed Pipeline-SAR ADC.The dynamic comparator circuit consists of a pre-amplification stage and a fast latching stage based on positive feedback.Compared with the traditional dynamic comparator,this comparator can shorten the transmission delay effectively.In the pre-amplification stage,PMOS is used as the input MOS to reduce the dependence on common mode voltage.In the latch stage,NMOS is used as the input MOS to effectively improve the working speed of the comparator.3.Complete the optimized design of circuit power consumption.Aiming at the design of residual amplifier,an improved dynamic amplifier is proposed in this thesis.Compared with the traditional closed-loop amplifier,the circuit works in the open-loop state,which can greatly reduce the power consumption of the circuit and improve the working speed.The dynamic amplifier can effectively solve the common gain instability problem of the open-loop amplifier,which makes the Pipelined-SAR ADC have good dynamic performance.In addition,by halving the gain multiple of the residual amplifier by interstage gain reduction technique,the power consumption of the whole circuit can be reduced again and the circuit design can be simplified.4.Complete the design of key modules and the overall circuit.In this thesis,bootstrap switch circuit,DAC capacitor array,SAR logic circuit and digital redundancy correction circuit are designed.Based on TSMC 40 nm COMS process,the circuit construction and layout design of the 12 bits Pipeline-SAR ADC are completed using Cadence simulation tool.The simulation result shows that under1.2 V power supply voltage,when the sampling rate is 160 MS/s,the input sine signal frequency is 73.8672 MHz,SFDR is 73.9 d B,SNDR is68.8 d B,ENOB is 11.14 bits,the power consumption is 5.26 m W,the core circuit area is only 0.029 mm² Its performance index can meet the design index.