Design Of Pipelined-SAR ADC Based On Dynamic Interstage Amplifier

Analog-to-digital converters(ADCs)are of crucial significance in the Internet of things(IOT)and signal processing.With the vital scientific advancement,a series of demands for higher sampling rate,resolution and power consumption of ADCs are proposed to meet the needs of the application environment.Pipelined-Successive Approximation analog-to-digital converter is brought into more focus than it has ever been by virtue of the quantization characteristic that is particular to the Pipelined ADC and SAR ADC.Curbed by the quantitative characteristics of SAR ADC,it is problematic attaining higher sampling rate for a Pipelined SAR ADC.In this paper,the working characteristics of the SAR ADC of the structure are investigated,and through the analysis of the working performance of different types of ADCs,this thesis prefers the SAR ADC of the double comparator structure as the sub-ADC,which is typical in its best comprehensive performance of speed,area and accuracy.Foremost,in this thesis,several kinds of inter-stage amplifier structures are analyzed,and it is decided to use the dynamic amplifier as the inter-stage amplifier.Futher more,the nonlinear error of the traditional dynamic amplifier is analyzed in detail,and an improved structure is proposed,which effectively solves the source of nonlinearity and provides better signal-to-noise distortion characteristics.In order to meet the precision requirements of ADC,this design uses a high linear bootstrap switch for sampling,and uses a two-stage dynamic comparator to effectively reduce the noise power of the comparator and improve the quantization speed of ADC.In this paper,full asynchronous timing control is adopted,which makes effective use of quantization cycle time.Finally,a 14-bit Pipelined SAR ADC is designed within the thesis under 40nm CMOS process with a power supply voltage of 1.1V.The Pipelined SAR ADC adopts three-stage with asynchronous timing control,and the residual amplification function is provided by dynamic amplifier in this paper.The simulation results show that when the sampling frequency is 250MHz,the input frequency is Nyquist sampling frequency and the input signal range is ±1V,all the process angles can reach more than 11bit,and under tt,ENOB=11.51bit,SNDR=71.02dB.The simulation results show that the improved dynamic amplifier proposed in this paper can effectively improve the linearity of ADC.