Dual-Mode Digital Background Calibration Technique For Pipelined Analog-to-Digital Converters

Modern wireless communications require high-speed high-resolution analog-to- digital converters (ADCs). Compared to other structures, pipelined ADC is more suitable for high-speed high-resolution applications, while faces more rigous requirements with the increased complexity of communication systems. Future CMOS technology brings more challenges to analog circuit design, which becomes the bottleneck of future ADC design. With the trend of system on chip (SOC) for integrated circuits, more and more digital circuits are used to calibrate and compensate the errors of analog modules. Among the existing digital-assisted-analog techniques, digital background calibration takes more advantages, since it tracks the temperature and power supply variation without interrupting the operation of analog circuit. For this reason, digital background calibration becomes one of the first choice techniques for future pipelined ADC design.The proposed thesis researched around digital background calibration for pipelined ADCs. Firstly, it analyzed the factors restricting the speed and resolution of pipelined ADCs and established mathematical models for circuit errors. Secondly, it overviewed and discussed the advantages and disadvantages of existing calibration techniques. Thirdly, it stated the principles of digital background calibration and analyzed the problems in existing digital background calibration techniques. Besides, it searched for the elements that deteriorate calibration performance and exported the relationship between the accuracy of the amplitude of persudorandom sequence and the resolution of pipelined ADCs.An input common-mode reference voltage generation technique for opamps is presented in this thesis. The input common-mode reference voltage is generated by the bias circuit that provides the static-state voltages for opamps, which gurantees the input transistors of opamps working at saturation region with corner, temperature and power supply variatation. By omitting the external buffers of input common-mode reference voltages, the proposed technique saves the power and area. A prototype of a calibration-free 12-bit 40-MS/s pipelined ADC with the presented technique is implemented in 0.18-μm CMOS technology. The measurement shows that at full sampling rate, with a 19.1-MHz input sine signal, the SNDR and SFDR achieve more than 67 dB and more than 80 dB, respectively.The thesis proposed a dual-mode digital calibration technique, which corrects the errors of the amplitude of the persudorandom sequence amplitude at ADC initialiton, and calibrates the interstage gain errors of the ADC by digital background calibration in ADC normal operation. Compared with the existing techniques, the presented method decreases the complexity of analog circuit, enhances the performance of digital background calibration, and improves the yield and resolution of pipelined ADC. Using opamps with low DC gains in ADC normal operation, the proposed scheme reduces the diffculties of analog circuit design and is more compatible with future CMOS technology.A prototype of 12-bit 40-MS/s pipelined ADC with the proposed dual-mode digital calibration is implemented. The first stage of ADC adopts an opamp with a telescopic structure and a DC gain of 58 dB in normal operation. The measurement shows that with the proposed calibration, the maximum INL decreases from 4.75 LSB to 0.65 LSB. At 40-MS/s sampling rate, with an input signal of 19.1-MHz, the SNDR and SFDR achieve 66 dB and 80 dB, respectively.