Research And Design Of A Hybrid Successive Approximation Register Analog-to-digital Converter

With the maturity of modern microelectronics technology and the development of IC industry,the integration of chips is increasing constantly.Compared with the large scale digital circuit,analog circuit is used relatively less,but it plays an irreplaceable role and position in many circuit systems.Unlike digital circuits that deal with logic levels,analog circuits are dedicated to the processing and application of continuous signals,and the analog-to-digital convertor(ADC)transforms the continuous analog signal recognition in the environment into discrete digital signals that can be processed by the computer.It has a wide range of applications in biomedicine,image recognition,security monitoring,information processing and so on.In this thesis,a hybrid SAR ADC is designed.In the digital to analog convertor(DAC)structure of SAR ADC,the C2 C structure and the binary weight structure(Capacity Binary Weight,CBW)are combined,the required capacitance of ADC capacitor array is significantly reduced,which greatly reduces the circuit area and the power consumption of the DAC module.At the same time,the corresponding calibration algorithm of the new ADC architecture is proposed,which can still have good static/dynamic performance after introducing sufficient capacitance mismatch and parasitism.This thesis proposes two C2C+CBW hybrid SAR ADC structures and calibration schemes suitable for different application requirements,which are verified by modeling and simulation.And choose the low hardware cost of the scheme,in the BCD process of130 nm,a 12 bit 1MS/s SAR ADC was designed,with C2 C capacitance structure for the lower six bits and binary distribution structure for the higher six bits.And the circuit design and simulation were completed.The power supply voltage was 1.5V.After adding transient noise of the circuit,the significant bits are 11.52 bits,SFDR 87 d B,SNDR 71.11 d B,and power consumption 111.84?W.Compared with traditional SAR ADC,the number of unit capacitors and DAC power consumption are both reduced by 98.43% under the same switching mode.