Research And Design Of High Speed Low-Metastablility Pipelined-SAR ADC

In recent years,with the development of smart phone,automotive electronic system,artificial intelligence system and other industries,the semiconductor industry has developed rapidly.ADC connects the digital world and the analog world.It is an extremely important circuit module in the field of integrated circuit.The quality and speed of signal transmission are closely related to its circuit performance,it is significant to study and design high performance ADC circuits.At present,the common ADC types are Flash ADC,Sigma-delta ADC,Pipeline ADC,Successive Approximation Register(SAR)ADC and so on.Pipeline ADC works in Pipeline mode and is widely used in high speed,medium and high precision applications.The structure of SAR ADC is simple,and it is widely used in high-speed and low-power applications.As the core module of ADC,the metastability of comparator will affect the whole performance of ADC,especially in highspeed ADC.In this paper,a 10-bit Pipelined-SAR ADC with high speed and low metastabilityrate is designed,which combines the advantages of conventional Pipeline ADC and SAR ADC.First,the metastability of the comparator is described,the factors affecting the metastability of the comparator are analyzed,and the published schemes to reduce the metastability of the comparator are summarized,Then,a scheme to reduce the metastability of the comparator is proposed,which uses two identical comparators and improves the logic circuit of the comparator and the capacitor array of the ADC.The feasibility and effectiveness of the scheme are verified by modeling.Then,MATLAB modeling is used to validate the ADC structure,and the basic structure of ADC circuit is determined by analyzing the simulation data.This design adopts two-stage pipeline structure,the first Sub-ADC is a 5-bit SAR ADC,and the second Sub-ADC is a 6-bit SAR ADC,including one redundancy bit.The Pipelined-SAR ADC circuit is implemented in CMOS 28 nm technology,the power supply voltage is 0.9V,and the performance of the Pipelined-SAR ADC circuit is simulated at 580 MHZ sampling frequency.When the input signal bit is Nyquist frequency,the effective bit of the circuit is 8.88 bit,the SFDR is 68.0 dB,the SNDR is 55.21 dB,the power consumption is 9.109 mA,and the FoM is 30 fj / conv-step.