Research On Calibration Technology Of Low-Power SAR ADC

Successive Approximation Register(SAR)ADC,as a high-resolution and lowpower Analog-To-Digital Converter(ADC),has been widely used in various fields.Compared to other types of ADC,SAR ADC has the advantages of high digitization,high energy efficiency,and simple structure,making it more suitable for advanced processes.The contradictory requirements of low power consumption,high speed,and high precision of SAR ADC also pose a series of technical challenges.Researching these challenges can help improve the performance and reliability of the entire mixed-signal system,and promote innovation and development in electronic technology.Capacitive mismatch is an important limiting factor of SAR ADC,which will have a negative impact on its accuracy.Without mismatch calibration technology,the effective number of bits(ENOB)of SAR ADC will be difficult to exceed 12 bits,even if a more precise capacitor array is used.This thesis focuses on the mismatch calibration tech-nology of SAR ADC and proposes an analog calibration algorithm.The algorithm uses redundant bits to extract the Differential Non-Linearity(DNL)error,determines the error polarity,and corrects the main capacitor array using the calibration capacitor array.The thesis models and verifies the algorithm using MATLAB,and analyzes its shortcomings,including stability,convergence,and search range.After further optimization for these issues,the algorithm achieves good calibration performance.This thesis designs a 14-bit 7 MS/s SAR ADC with a power supply voltage of 0.9 V in the 28 nm process,and further verifies the algorithm.The circuit structures used in each module are described in detail,and performance optimizations are performed separately.Finally,the MATLAB-corrected capacitor array is used for simulation in the original circuit.After calibration,the ENOB of the ADC is 12.22 bits,and the Signal-to-Noise and Distortion Ratio(SNDR)and Spurious-Free Dynamic Range(SFDR)are 75.32 d B and85.01 d B,respectively.The ADC core power consumption is 130.5 μW,and the Figure of Merit(Fo M)value is 3.9 f J/conv-step.