Research And Design Of High-speed Successive Approximation Register Analog To Digital Converter

ADC(analog-to-digital converter) is the most significant partment in many electronical implements.SAR(successive-approximation)ADC is used widely for its simple architecture, prominent power efficiency and small chip die and is researched widely in recent years.This dissertation introduces the foundametal theory and operating method of the SAR ADC and analyse how the mismatch of each capacitance effect the performance of the converter firstly.secendly,present how to design a 10-bits, 10MS/s charge-redistribution SAR ADC with a redundancy, operation voltage 3.3V and differential input from 0.25*VCC to 0.75*VCC and present the analyzing and testing results: the SNDR(signal-to- noise-plus-distortion ratio) is 59.99 d B, the ENOB(effective number of bits) is 9.67 bits.,the most worse DNL(differential non- linearity) is 0.48LSB(least significant bit) and the most worse INL(integral non-linearity) is 0.61 LSB.The accuracy of this converter is always restricted by the match of its internal capacitance array. In order to obtain a better accuracy, in general, a bigger capacitance must been used,but this limits the rate of the converter. So the paper studyed many different calibration technique,analysed their merits and demerits and presents a new technique for calibrating the mismatch of each capacitance. This increased the speed of the converter obviously.Using the new calibration technique,this paper designed a 100MS/s SAR ADC,including the analog circuit and the Verilog-HDL code of the digital calibration operation. Optimized the layout plan of the capacitance array, this decreased the parasitic capacitor and getting a better linearity. Verified the digital calibration algorithm by Matlab.Finaly,simulated the analog circuit and calibration algorithm using Finesim and NC-verilog. At 100MS/s, the converter has a SNDR 60 d B and ENOB 9.7bits.