Research And Design Of High Speed Folding And Interpolating ADC Based On InP HBT Technology

Analog-to-digital converter(ADC)can convert analog signals to digital signals that are easy for computer processing,and plays a vital role in signal processing systems.As people increasingly pursue fast processing of information,high-speed ADCs have become an important branch of analog-to-digital converters.Folding and interpolating ADCs have signal processing speeds comparable to full-parallel ADCs,while their circuit scale and power consumption are relatively small,making it an important research object in high-speed ADC.Since the heterojunction transistor(HBT) has a higher cut-off frequency than the CMOS transistors,they are widely used in the design of ultra-high-speed ADCs.Therefore,based on the 1.5um In P HBT process,this paper designs a high-speed folding and interpolating ADC with a conversion accuracy of 8bit and a sampling rate of 6GHz.This ADC adopts fully differential circuit structures and is designed with only NPN transistors.The overall architecture of ADC is 3-bit coarse quantization and 5-bit fine quantization.The main circuits include sample-and-hold circuit,coarse quantizer and fine quantizer,among which the fine quantizer includes a folding and interpolating circuit,comparator circuits and a fine quantization coding circuit.Since the current amplification factor ? of the transistor used in the process is small,the base current is too large under the same emitter current,and the excessive base current of the folding amplifier flowing into the reference resistor string will affect the accuracy of the zero-crossing point,thereby affecting the effective number of bits of the ADC.In view of the base current problem,the folding amplifier has been improved to some extent.An emitter follower circuit is added between the folding amplifier and the reference resistor string.The tail current of this emitter follower can be designed to be relatively small,so its base current is also will be relatively small,thereby reducing the zero-crossing deviation caused by the base current.In the comparator circuit,a pre-amplification circuit is added and a two-stage latch circuit structure is used.This not only improves the ability of the comparator to distinguish small voltages,but also effectively improves the metastability of the comparator and improves the comparator's nosise performance.In the fine quantization coding circuit,the thermometer code output by the comparator may produce wrong code words.In order to reduce the bit error rate of the comparator,a bubble error correction circuit is adopted.The designed ADC needs to be simulated and verified.Under the conditions of a sampling frequency of 6GHz,a power supply voltage of 5V,an input signal full swing of 1.6V,and an input signal frequency of 500MHz,the pre-simulation results show that the ENOB of the ADC is 7.33bit.The ENOB of post-simulation is 7.07bit,and the total power consumption of all circuits is 13W.