Design And Research Of High Speed Folding And Interpolating Analog To Digital Converter

As an important module of wireless communication, computer technology and digital processing technology, Analog to digital converter has broad application prospects and market in software radio, high-speed data acquisition systems, high speed digital mobile communications and high-end measuring instruments and so on. Folding and Interpolation analog to digital converter inherited the full parallel analog to digital converter speed advantage, which uses a parallel two-step quantized structure, while the fine quantization channel circuit with folding and interpolation techniques to reduce hardware costs and power consumption of the circuit, thus folding and interpolation architecture with fully parallel architecture similar conversion rates, while the area and power consumption are better than all-parallel structure.In this thesis, a single channel 8bit 1.25GS/s folding and interpolating analog to digital converter is designed under the TSMC0.18μm CMOS technology. Due to as the first stage of the analog preprocessing circuit, sampling holding circuit’s sample rate and linear degree determines the analog to digital converter’s sample rate and the resolution, this paper uses the two-stage pipelined main sample and hold circuit, by increasing the sample rate, linearity and hold time, the maximum sampling rate and the maximum resolution of the analog to digital converter is improved; using a two-stage cascade folding and interpolating structure. This structure in the realization of large folding and interpolating factor while maintaining circuit high bandwidth; using folding pipelined architecture, between the two levels of folding circuit inserted between the sample and hold circuit so that they can be processed in parallel signal. The basic structure is improved by using the technique of cascade offset averaging. In the circuit design, this paper completes the design of the unit circuit of sample holder, preamplifier, folding and interpolating circuit, and comparator. Through the deep research of each unit circuit, the design of the whole system is finally realized. The design and simulation of each key circuit module is completed in Cadence IC platform, and each unit circuit noise and offset are analyzed. The whole circuit occupies 1.5x1.4mm2. The SNDR is 46.56dB, SFDR is 57.59dB and ENOB is 7.442bit at 1.25GS/s sampling rate, and the power consumption is 336mW.With the rapid development of microelectronics technology, the wide application of high-speed large scale integrated circuit, system in the high speed circuit design also has been paid more and more attention, this topic design an application at 1GS/s, 8bit resolution high-speed analog to digital converter data acquisition module, completed the data acquisition module design, detailing the implementation of the hardware system, and using Xilinx ISE software ChipScope Pro tool to save data after sampling on this basis, and its FFT analysis. ChipScope Pro software to grab through the output data to calculate the SNDR is 35.9246dB, SFDR is 40.6882dB, and ENOB is 5.5631bit. Test data show that high-speed data acquisition module with good performance in 200MHz, can be used for further processing.