Design Of High-speed, Low-power, Low-voltage Folding And Interpolating ADC

High-speed ADCs, especially with the sampling rate of more than 500 MS/s are widely used in many systems such as ultra-wide band, read-write channels in data storage systems and digitizers in high-speed digital oscilloscopes. In UWB systems, ADCs with sampling rate of 1 GS/s and resolution of 5-6 bit are needed; in read-write channels, ADCs with sampling rate of more than 1 GS/s and resolution of 6 bit about are needed; in high-speed digital oscilloscopes, ADCs with sampling rate of more than 1 GS/s and resolution of 8 bit are needed. For embedded applications, design concerns of high-speed ADCs are focused on low power and low voltage; in high-speed instrument applications, design concerns are focused on the optimization of speed.Based on the above research background, the speed optimization and the design method for low power and low voltage of folding and interpolating ADCs are proposed in this dissertation. The main contributions of speed optimization are concluded as follows:(1) An inter-stage pipelined structure is presented in order to reduce the critical path of analog preprocessing. It is useful to improve the sampling rate of ADCs. A dual-diode bootstrapped inter-stage sampling switch is proposed. The area of the switch is smaller than the traditional one. It is suitable to use in large-scale sampling switch array.(2) A cascaded offset averaging is proposed. The averaging resistors are moved from the outputs of the preamplifier array to the outputs of each stage of cascaded folding amplifiers so that the connection complexity between the preamplifier array and folding amplifier array is simplified. It can help reduce the time of analog preprocessing.The main contributions of design for low voltage and low power are concluded as follows:(1) A method of fine/coarse joint encoding is presented in order to reduce the hardware consumption of the coarse sub-ADC. It is helpful to optimize the power of ADCs.(2) A preamplifier with rail-to-rail input is proposed so that the input signal amplitude of the preamplifier can be increased. It is beneficial to overcome the impact of offset under low supply voltage.(3) The ratio of the load resistors of the cascaded folding amplifiers is optimized. So the gain-bandwidth of the cascaded folding amplifier is maximized.(4) An input-connection-improved active interpolating amplifier is presented. By changing the input connection, the linearity of the active interpolating amplifier is improved under low supply voltage.(5) A comparator with dummy reset switch is presented. The dummy reset switches are useful to reduce the dynamic offset of comparators.According to the proposed optimization and design methods, two design cases are implemented in 0.13-μm,1.2-V/2.5-V, single-poly, eight-metal mixed-signal CMOS technology.(1) A 600-MS/s 6-bit folding and interpolating ADC is implemented. By using this ADC as channel ADC, a 1-GS/s 6-bit dual-channel time interleaved folding and interpolating ADC is also implemented for MB-OFDM UWB system.(2) A 1-GS/s 8-bit inter-stage pipelined folding and interpolating ADC is implemented for digital oscilloscopes.The measurement results show that:(1) The 1-GS/s 6-bit dual-channel time-interleaved folding and interpolating ADC achieves DNL of 0.57 LSB, INL of 0.81 LSB, ENOB of 5.18 bit with the input frequency of 1 MHz and ENOB of 4.8 bit with the input frequency of 500 MHz. The power consumption is 66 mW with the sampling rate of 1GS/s. FoM is 1.75 pJ/convstep. It is the second best compared with some 6-bit ADCs of similar sampling rate published from 2001 to 2007. The ADC core occupies 0.45 mm2.(2) The 1-GS/s 8-bit inter-stage pipelined folding and interpolating ADC achieves DNL of 0.76 LSB, INL of 2.46 LSB, ENOB of 6.61 bit with the input frequency of 2.4 MHz and ENOB of 6.13 bit with the input frequency of 400 MHz. The power consumption is 110 mW with the sampling rate of 1GS/s. FoM is 1.26 pJ/convstep. The ADC core occupies 0.32 mm2. The sampling rate of 1 GS/s is the highest in the published single-channel folding and interpolating ADC by far.