Research And Design Of High-Speed Folding And Interpolating Analog To Digital Converter

High-speed analog-to-digital converters(ADCs)have a wide range of applications which involve radar,satellite communications and so on.In recent years,with the rapid development of 5G communication technology,people demand more and more high-speed ADCs and put forward higher requirements on their performance.Folding and interpolating ADCs can play a big role in these areas since they have high speed,medium accuracy and power consumption on which their advantages rely.In this paper,the architectures of several high are firstly analyzed and compared,then their performance is summarized and compared.Afterwards,the principle and design of the folding and interpolating ADC are described in detail.The input signal is sampled and held by using a track-and-hold amplifier with a gate-voltage bootstrap structure.By applying a constant voltage to the source of the switch gate to suppress the change of on-resistance,the non-linearity during sampling is suppressed;Since the pre-amplifier is at the front of the analog circuit,its offset will be further amplified due to back-end circuit,and in order to suppress the offset,resistance average technology is applied;In order to achieve a large folding factor without affecting the bandwidth of the folded circuit,a two-stage cascade folding method is adopted instead of the single-stage folding method,and in addition,the track-and-hold amplifier between stages can relax the requirement of the bandwidth of folding circuit;In order to improve the accuracy of zero-crossing points and the linearity of ADC,the interpolation error caused by the resistance interpolation is suppressed via adjusting the parameters of the circuit,and the amplitude mismatch between the interpolation curve and the folding curve is suppressed via improving the interpolation network;In order to reduce the kickback noise of the high-speed comparator,the circuit structure is improved and the offset is suppressed via adjusting the circuit parameters.Finally,the schematic design and layout design of the folding and interpolation ADC are completed under TSMC0.13?m CMOS process.In the schematic design,each module has been individually simulated to make its parameters achieve the desired goals,and finally the overall pre-simulation has been passed.On this basis,layout design,parameters extracting and post-simulation have been completed and the chip area reaches 1.9*1.4mm~2.The post-simulation results show that the SNDR,SFDR and ENOB are 45.41dB,49.93dBc and 7.25bit respectively at the sampling rate of 1.5GHz and the signal frequency of 64MHz.The total power consumption is 175mW.In this paper,the design and implementation of a high-speed ADC measurement platform are also introduced.Taking chip ADC12D1800 of ADI of which the architecture is folding and interpolating as an example,the measuring process of high-speed ADC is introduced in detail.The correctness of the measurement platform and the measurement method are verified by comparing the measurement results and the manual indexes.The above content is instructive for the measurement of the folding and interpolating ADC in the future.