High Speed Folding And Interpolating ADC Design

With the development of the mobile multimedia, the high speed, low power and small area analog to digital converter (ADC) are becoming more and more important.This dissertation mainly to study and design a high speed, low power and middle resolution ADC, uses folding and interpolating structure. Folding structure ADC has the high speed characteristic, by means of analog preprocessing circuit to reduce the number of comparator and the circuit complexity, at the same time, it reduces the power and chip area. Furthermore, folding ADC employing the interpolation schemes to generate extra folding waveforms, it also can cut down the chip power, area and keep the high speed.This whole circuit use fully differential structure, it reduces the system noise and enlarges the input voltage effectively. A distributed sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADC. Optimizing the folding amplifier design, and employing the resistor interpolating to reduce the power consumption. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels.The design bases on UMC 0.18um CMOS technology, the whole ADC consumes 130mW with a single 1.8v supply at 200Mhz conversion rate. Simulation results show the ADC can achieve SNDR above 40dB at 97MHz input frequency.