Research And Design Of Ultra-low Power SRAM Circuit Applied To Image Processing

Static random access memory(SRAM),as an important part of So C,is widely used in low-power applications such as handling electronic equipment,sensors,and medical devices.Since the dynamic power consumption is squared with the supply voltage,lowering the supply voltage can significantly reduce the system power consumption.However,due to the challenges faced by SRAM cells under low voltage,simply reducing the supply voltage can no longer meet the needs of ultra-low power consumption.Therefore,in some applications that can tolerate the errors of low-order bits,such as image and video processing,big data,and neural networks,using approximate SRAM structure can further reduce system area and power consumption.This article outlines the methods of ultra-low power SRAM,which are cell stability design and approximate structure design under low voltage.Based on the existing research and design of ultra-low power SRAM circuits,this paper proposes an ultra-low power SRAM circuit that uses the cell structure design method of approximate structure for image processing.In a word of SRAM circuit,the high and low orders bits adopted different cell structures.The high-order cells adopt a relatively high-stability cell structure to store the high-order of pixel data,while the low-order cell has a relatively low stability of the high-order,so as to reduce the power consumption and area of the system.The important parameters of the high and low bits of the SRAM circuit are compared with various cells through simulation.At the same time,Monte Carlo simulation of noise tolerance and write margin is performed to obtain the error rate of high and low bit cells.This paper builds an 1kb approximate SRAM circuit,and designs a new type of sense amplifier circuit to solve the problem of single-ended read operation structure SRAM under ultra-low voltage.Afterwards,the overall SRAM array circuit is simulated and verified,and the results showed that the SRAM circuit can achieve correct retention and read/write operations.When at the minimum operating voltage 0.5V,the maximum operating frequency of the SRAM circuit is about 250 MHz under the conditions of TT process and 25°C.When simulating the performance of the circuit with image processing,according to the error rate of the high and low bit cells,we use MATLAB to insert random errors into the image.At the same time,the circuit performance,area,and power consumption are traded-off.In an 8-bit word of the SRAM circuit,the number of high-order bits is 3 and the number of low-order bits is 5.The area of the cell array is only increased by about5.77% compared to the pure low-bit SRAM circuit cell array.The best operation voltage is between 510 m V and 520 m V.Within this voltage range,the average dynamic power consumption of the circuit is increased by about 15% compared to the pure low-bit SRAM circuit,while the image performance increased by more than 55%.A significant performance improvement is achieved while a small area and relatively low power sacrifice.