The Design And Implementation Of High Speed Sense Amplifier Based On65nm SRAM

Sense amplifier (SA) has been widely used in several digital and analog circuits, such as memories (SRAM, DRAM, and Flash), A/D converter, data transmitter and receiver and so on, due to it can detect and amply the small differential signal to a full swing signal. According to different application, the structure of SA is slightly different. In order to improve the speed of SRAM, this thesis focus on the sense amplifier, which is one of the most important peripheral circuits in the SRAM. Furthermore, this thesis proposes a new kind of sense amplifier and a new offset reduction technique to improve the speed of SA and the whole SRAM. Finally, this thesis applies the offset reduction technique to a high speed SRAM which with512words×32bits.The major metrics for sense amplifier design are offset, speed, power, area and yield, during which the offset may be the most important parameter. As the scaling of semiconductor technology, the process variations would cau,e even more device mismatches, which in turn would make the sense amplifier fail to amplify the small signal into the correct value. Therefore, it raises a higher requirement for the sense amplifier design.Firstly, the thesis analysis the key and difficulty of sense amplifier design under advanced process. Secondly, it elaborates several kinds of typical sense amplifier, and based on the analysis, a new structure sense amplifier was proposed. The simulation results under SMIC65nm process show that the time of forming the differential voltage is minimum, which can be reduced by18.26%compared with others. When amplify300mV differential voltage under the same condition, the time and power consumption consumed by the proposed SA can be reduced by25.62%～50.38%and18.31%～27.72%when compared with the structure one, and when compared with the structure two, the time and power consumption was reduced by47.56%～58.72%and19.63%～44.98%. A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this thesis. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by31.23%(StrongARM SA) and25.17%(Double-tail SA), respectively, when the voltage of enable signal reaches0.6V in SMIC65nm CMOS technology. For a column of bit-cell (1024bit-cell), the total speed is improved by14.98%(StrongARAM SA) and22.26%(Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by30.45%and29.47%with this scheme. Finally, the offset reduction technique proposed in this thesis was applied to a16kb SRAM to verify its effectiveness, the Tcq of pre-simluation result was226.1ps～644.3ps and the post-simulation was644.1ps～1120.2ps, they were both smaller than1.25ns, the pre-and post-simulation results demonstrate that the performance of16Kb SRAM can fully achieve the goal requirement.