Low Power SRAM Design And Implementation In X-DSP

Accompanied with the lasting increasing of the IC's intensity and operating frequency as the Moor's law, high performance and low power designs become the mainstream of chips.The memories have taken an absolutely large part of area on DSP, and the tendency is still going on.The consequence is the increase of length of wordlines and bitlines in memories, and delay and power. How to optimize the performance and reduce the power of the memory is the key of the DSP.Based on the study of low-power design technology,this paper designs and optimizes the SRAM of X-DSP in low power, respectively at system level and circuit level. The memory is partitioned into several banks and the word lines are divided to reduce the load capacitance and then reduce theirs power. Research a improved word line pulse technology, the clock signal is divided into multiple segments to decrease the amplificatory time of the sense amplifier and then to reduce its power.The decoder uses three-level static coding,design a storage circuit which consisted by the read and write control circuit whose bit-line swing can adjust and basic memory cell. As a result, the power is greatly optimized.We design a SRAM under the process of 0.25μm CMOS with full custom. The full flow includes logic design, layout design, BIST design and verification after sign off. The memory, decoder and sense amplifier circuit are designed and optimized. Simulation results indicate that read/write performance and power consumption of the SRAM designed in this paper have improved greatly.The Starsim simulation in typical case, the data reading time is 2.49ns, the data writing time is 1.40ns, and the maximum power is 96.32mw. Compared to the SRAM which is generated by the memory compiler,the designed SRAM's access time reduces by more than 26% and the average power consumption readuces by more than 30%. The system using our SRAM works well, meanwhile the performance and the power meet the design requirements.