Fluctuation Features Research Of SRAM Sense Amplifier Timing In 65nm CMOS Process

As the mobile internet devices become more popular and all kinds of consumer electronic products develop rapidly, the speed, power consumption and area of SOC are the keys to the demand of the market. Process from the mainstream of 180 nm to 28 nm or less, increase transistor response speed and chip integration, and increase the transistor threshold voltage fluctuations, and also bring a challenge to the traditional designs of SRAM. In order to improve the timing volatility, we put forward two novel dual replica bitline circuit structures finally, which improving the speed of SRAM read operation, and reducing the power consumption and the area. The main work and innovations of this paper are as follows:First of all, we analyze the SRAM cell composition and working principle, and then point out the SRAM read operation as the timing of the critical path, and analyze the importance of timing stability and significance of the research, and then introduce the traditional clock circuit structure, and compare the replica bitline delay line and an inverter chain delay according to the point of view of statistics. Through Monte Carlo simulation, in a 65 nm CMOS process, it verifies that the replica bitline delay technique can be very good to depress the sensitive amplifier timing fluctuations.Secondly, we analyze the working principle of some replica bitline techniques proposed by the experts at home and abroad in recent years, such as multistage replica bitline, digitized bitline, dual replica bitline and so on. Introduce the circuit structure and working principle in detail, and analyzes their respective advantages and the existing problems.Finally, in this paper, we propose the multi-stage dual replica bitline with combination of existing technologies and two novel replica bitline circuit structures. Their circuit structure and working principle are introduced in detail, respectively. On the basis of not using the auxiliary circuit and not increasing the size of the layout area, we connect left side of the replica bitline and the wordline of the right side of replica bitline through an inverter. So standard deviation is reduced to about 50% compared of conventional technique, so as to obtain an optimized timing signal, and also avoid the extra power waste and shorten the SRAM clock cycle effectively. Montecarlo simulation results under different PVT conditions show that the proposed replica bitline circuit can reduce the SAE timing fluctuation deviation to about 50% theoretically.