Embedded High-Speed Low-Power SRAM Design And Optimization

With the continuously improving of the microelectronics craft technique level, embedded SRAM present a trend of the higher integration, higher speeding and lower power. In recent years, it's not fresh of that you can see the various system chip of the integrated SRAM anywhere. These chip have positive effect in the aspects of improving the system function, raising the chip reliability and lowing dissipation power, etc.. This text mainly describes the design of the embedded synchronous dual-port SRAM. Based on the analysis of the SNM and SER, 8T cell are optimized, which not only reduce cell size(the memory cell size: 5.87×6.54um2)but also make the SRAM more reliable(SNM8T=530mv).At the time of designing every parts of the SRAM circuit, how to low the power and raise the speed was considered carefully. For example, the usedge of the three-rated sense amplifier can raise the speed of reading. The design introduced the arbiter logic to solve the problem Judge the storing priority of two inputs. The access time can keep within 2.96ns. We used the structure of desequencing-decoder memory array and interval-decoder memory array in the design of the layout of the memory array for minishing the disturb problem and raising the reliability. The chip is fabricated by a double polysilicon, four metal and twin-well 0.18um CMOS process technology, and the chip size is 746.36×966.74um2. The SRAM word length is 28 bits.