Based On The 65nm Technology Platform, Low-power Embedded Sram Design

As demands for increasing performance and features are being placed upon semiconductor designers, the amount of on-chip memory continues to grow. Base on the estimation, embedded memory will occupy 90% area of the whole chip by 2014. So the density, speed and power consumption of embedded SRAM become more and more important in system level IC design. Selecting the most optimal embedded memory for the application is becoming progressively more critical to avoid performance "bottlenecks", reduce system power consumption and cost.With the increasment of integration and speed of IC, the power per area is becoming more and more serious. In order to optimize the power consumption, enlarge the working time of mobile device in battery mode and reduce the package cost. Designer must take special consideration in the power while designing a product.In recent years, the SRAM development trends can be summarized as fast speed, large capacity and low power. In this paper a 64Kb embedded full-CMOS SRAM is described. The design is based on the 65nm low power process. In order to improve the speed of the eSRAM, array partition, divided bit line structure and the positive feedback sense amplifier and dynamic logic are adopted. The access time of SRAM in typical condition is about 0.717ns. How to reduce the power is the key target in design, so we use the multi-block architecture and self-time reset methodologies to optimize the dynamic power consumption. Apart from that, the power gating techniques are used to control the leakage power of the chip. The simulation result shown 38% reduction is obtained. This project also provides the redundancy solution to repair defective bitcells, which is very import to improve the chip yield.