Study Of High-speed Low-power Embedded Sram Design

With the improvement of semiconductor manufacturing process and IC design capability, various types of circuits including processors memory,analog circuit,I/O logic and RF(radio-frequency) circuit have already been integrated into one chip, which is called SoC (system-on-chip). By statistics, as an important part, Embedded memory gets a growing area proportion in SoC, which increases from 20% in 1999 to 60%-70% in 2007, and will be 90% in 2014 by estimation. Hence we can see that embedded memory plays a critical role in the whole chip. Embedded static RAM is a well known embedded memory due to its low power consumption, fast speed and stability. It can help to improve system performance and reliability, and lower the cost and power consumption.In this paper,128Kbit(4Kx32) embedded static RAM is used as an example to describe how to design a low power embedded static RAM. Advanced 65nm process is used in the fabrication of the memory. Advanced technologies, such as dynamic CMOS decoder which using SCL(source-coupled-logic) circuits, pulse signal technology, latch type voltage sense amplifier, power gating, memory array segmentation are used in the design. SCL dynamic CMOS interpretation circuit not only speeds up the interpretation, but also occupies much smaller area than traditionally used interpretation circuit. Pulse signal technology can reduce enabling time of word line, bit line and peripheral circuit, so that can improve system performance and lower power consumption. Latch type voltage sense amplifier can not only speed up read/write but also cut down the power consumption. Power gating reduces the static power consumption by 47%. Memory array segmentation localizes the signal, which reduces the switched capacitor. As a result, the delay and power consumption can be reduced. However, memory array segmentation will lead to the increase of the chip area, as well as delay due to too much connection. So using memory array segmentation too much will cause the decrease of memory performance. When memory array segmentation is used, performance should be taken into consideration so that an optimum hierarchical structure can be achieved.