Design Of A Novel Structure Of Sense Amplifier And Address Decoder Applied In A SRAM

Semiconductor technology has advanced rapidly since the first transistor appeared in 1950s. With the advent of Ultra Large Scale Integrated Circuit (ULSI) era arrives,the semiconductor technology has been the cornerstone of whole information age. Following enhanced process technology,as the feature size of a device becomes smaller,the semiconductor density increases and,at the same time,performance improves dramatically. Undoubtedly,the 21st century will be the century of information,as semiconductor technology will play a cornerstone role. In the large family of semiconductor technology,static random access memory (SRAM) attracts much attention because of its broad applications. SRAM has become an indispensable member of semiconductor memory family due to its low power consumption and high-speed performance. Its usages in today's computer,communication,and consumer electronics are wider and more popular.This thesis first describes the structure and operational principle of a SRAM. The commonly used structures of SRAM peripheral circuits,sense amplifier and address decoder,were analyzed. Second,a novel structure design of sense amplifier and address decoder applied in a 3.3V full-CMOS 16Kb SRAM is illustrated in detail. Third,simulation results of the above design using CSMC 0.6um process technology under various conditions will also be provided.