The Research And Design Of A High-Speed, Low-Power 4M Bits SRAM

A large portion of the silicon area of many contemporary digital designs is dedicated to the storage of data values and program instructions. More than half of the transistors in today's high-performance microprocessors are devoted to cache memories, and this ratio is expected to further increase. Depended on its fast access speed and its low power, Static Random Access Memory (SRAM) is a great part of the memory family. SRAM have been implemented in many high-tech chips involving multi-media, compressing and decompressing of video signals, transferring TV signals, digital orbiter system and etc. The high-speed and low power SRAM has become a hot research area in today's digital research fields. In this thesis, A high-speed and low-power 4M bits asynchronous SRAM were designed on discussing its related design techniques.Firstly, The architecture of objective 4M bits SRAM were designed on the analysis and comparison some basic SRAM's architecture. A fully structure and detailed circuits were presented and discussed. Secondly, the SRAM 6-T cell were analyzed in detail involving the structure, the operating principles. The optimum cell size were determined on the basis of hundreds of simulations which focus on the operating stability and layout area trades off with SMIC 0.25μm technology. Thirdly, A high-performance Sense Amplifier (SA), which is able to amplify the tiny differential signal to full power rails in 0.5ns at the worst case, were designed on the analysis and summarization of three types of basic SA structures. At last, from carefully simulation of the whole circuits , it is estimated that the typical parameter were that the access time is lower the 20ns, the average operating power consuming were nearly 30mV and the standby power consuming were about 0.25mW.At the same time, the thesis presented a new heuristic design method for design the sizes of a CMOS logic chain with fixed long interconnect wire. The simulation proved that the decoders using the design methods can save 20% power and 15% layout area than it designed with the traditional methods.The designed SRAM's access time and dissipated power have reached the same time of the same type of the oversea products, only it's layout area are a little larger than them, which were produced with advanced processing technology. Therefore the design technology analyzed in the thesis were proved to be right and successfully and can be referenced in the future design.