HSPICE Simulation And Design Of Sensitive Amplifier Module For SRAM Memory

Microelectronic technology has advanced rapidly since the first transistor appeared in 1950s,and now we are in the era of VLSI and system integraton .Microelectronic technology has been the cornerstone of whole information industry . In the large family of semiconductor products,semiconductor memories attract much attention because of its broadapplications . Static random access memory(SRAM)has become an indispensable member of semiconductor memory family due to its low power consumption and high-speederformance.Following enhanced process technology,asthefeaturesizeof device becomes smaller,the storage ability of SRAM increases continuesly,and at the same time , its perafrmance performance hasbeen improved dramatically.It is still an important researching topic in IC design field to raise and to improve SRAM performance. For the purpose to reduce the SRAM power dissipation,and based on the study of the working mechanisms and the structure of sensitive ampifier used as the keymodule of SRAM,this thesis proposed and implemented an improved Latch-stylesensitive amplifier,Hspice simulation indicates that its power dissipation is muchlower than that ofthe triditional sensitive amplifier used in SRAM. This thesis consists of four chapters.The first one summarises the classification and the current developing state of SRAMs at home and abroad.Chapter two gives a short introduction EDA tool---Hspice,a main simulation tools used in this work.The next chapter is the keystone to accomplish the prpose mentioned above,in wchich a deep understanding and a tedailed analysis of SRAMs'basic structures and theirdistinguishments areperformed.After finishing these necessary preparations,three kinds of senseamplifiers,used as SRAM'S key modules,are analyzed in chapter four, mainlyfocused on their tructures and operational mechanisms,and then simulated byHspice, in order to compare their advantages and disadvantages.Then,anovelstructure of sensetive latch-style-improved amplifier,in the view point ofpower dissipation, is proposed,and Hspice-simulation results of the design are also provided in details . Hspice-simulation results indicate that the performance of thesensetive latch-style-improved amplifier has been improved , its power dissipation ismuch lower than that of the traditional sensitive ampifiers used in SRAM , with an almost unchanged raising time. The last part of this thesis is a conclusion,companing with some looking forwardand suggestion to continue this work.