Research And Design Of High-Resolution SAR ADCs Based On Noise Shaping

Analog-to-digital converters(ADC)is a necessary module in wireless communica-tions,medical electronics,industrial control,etc.Its basic function is to convert the con-tinuous signals existing in nature,such as sound,light,and electricity,into discrete digital signals that can be processed by computers.The rapid development of electronic industry has put forward higher requirements for the performance of ADCs,such as speed,accu-racy,and power consumption.Successive approximation register(SAR)ADC has the advantages of simple struc-ture,high digitization,low power consumption,small area,and high process compatibil-ity.It has been widely concerned and applied by academia and industry.However,the accuracy of the traditional SAR ADC is usually limited to 8-10 bit.In high-precision applications,such as sensors,audio,etc.,the ?? modulator is usually used,but high sam-pling rate and high gain active integrator are required to attenuate sampling noise and quantization noise.As a hybrid combining of the SAR structure and the ?? modulator structure,the noise shaping SAR ADC exhibits the advantages of low power consumption and high precision,and has attracted more and more attention.In this paper,the basic theory,system architecture and key technology of noise shap-ing SAR ADC are studied and analyzed,and a first-order passive noise shaping SAR ADC is designed.This thesis first explains the principles of oversampling and noise shaping used in high-precision design,and analyzes the advantages and disadvantages of active and passive noise shaping.In this design,the energy-efficient passive shaping method is adopted.Secondly,in view of the large input referred noise of the multi-input comparator in the passive noise shaping SAR,this thesis adopts a dynamic bias structure with lower power consumption and lower noise.Finally,this thesis has completed the overall circuit design and simulation of the noise shaping SAR ADC under the 180 nm CMOS process.The power supply voltage of this design is 2 V,the sampling frequency is 20 MHz,the SFDR of 81.37 d B is realized in the bandwidth of 1.25 MHz,the ENOB reaches 12.56 bits,the power consumption is 795.6 ?W,and the Fo M reaches 169.38 d B.