Research On Key Techniques Of Noise-Shaping Based Energy-Efficient Analog-to-Digital Converters

Analog-to-digital converter(ADC)is an integrated circuit(IC)which transforms a signal from analog to digital form.Since most real-world signals are analog,ADC is an essential component in modern electronic devices and can find wide applications as a bridge between the analog world of transducers and the digital world of signal processing and data handling.In recent years,driven by the market demand featuring the applications of Internet-Of-Things(IOT)and by advancement in IC manufacturing technology nodes,ADCs become faster and smaller with higher speed and lower power consumption.However,IC technology scaling also brings great challenges to ADC circuit design:(1)the supply voltage of transistors becomes lower,resulting in reduction of ADC dynamic range and signal-to-noise ratio(SNR)directly;(2)it is hard to realize high-performance amplifier with lower supply voltage and smaller transistor intrinsic gain,which has become the bottleneck for high-resolution ADCs relying on amplifiers with high gain and linearity;(3)devices mismatch problem is more severe with smaller feature size,causing serious non-linear distortions to ADCs.Due to these issues,both the academics and industries start to seek creative solutions over the traditional design techniques.Recently,the hybrid structures,digital and passive circuits become the popular trends for ADC designs.A successive approximation register(SAR)ADC consists of switched-capacitor circuits,a dynamic latch-based comparator and some digital logic circuits.Thanks to the highly-digital and highly-passive circuit structure,the SAR ADC is scaling friendly and benefits tremendously from the advancement of technology nodes.Traditional SAR ADCs are one of the most energy-efficient ADC architecture in low-to-medium resolution field,however its energy-efficiency decreases dramatically in high-resolution applications due to the restrictions by comparator noise and device mismatch.It has become an urgent key technique on how to improve the energy-efficiency of SAR ADC while maintaining its merit of scaling friendliness.This dissertation makes a comprehensive study on the design techniques and non-idealities of SAR ADC,analyzes the principle and methods to improve ADC's energy efficiency,proposes two noise-shaping based ADC architectures and a mismatch error shaping(MES)method which can significantly reduce the in-band noise and mismatch error,and realizes high-resolution ADCs wtih high energy efficiency.The main contributions of this dissertation are as follows:1.We propose a new second-order fully passive noise-shaping SAR ADC architecture,which uses the switched-capacitor circuits to realize the second-order noise shaping.The noise-shaping SAR ADC has strong shaping capability,it can efficiently reduce the in-band quantization and comparison noises by 24 d B,thus significantly improves the resolution and energy efficiency of the ADC.It has only two switches,two capacitors and two additional comparator input pairs on top of a classic SAR ADC.Comparing to previous noise-shaping SAR ADCs,this architecture reduces the attenuation of passive integration path,resulting in 2.4 times reduction in capacitor area and 40% reduction in comparator power.It does not require any active circuits including the operational transconductance amplifier(OTA),thus has no static power.The proposed noise-shaping SAR ADC is compact and robust against the variations of process,supply voltage and temperature(PVT).It is well suited for the IOT applications which require ADCs with low power and small size.Fabricated in 40 nm CMOS process,the 5-bit second-order noise-shaping SAR ADC measures 9-bit effective number of bits(ENOB)and 35 MHz bandwidth with 560 MS/s sampling rate and OSR of 8.The total power is 0.64 m W,and the active area is only 0.0035 mm~2.2.We propose a new ?? ADC with noise-shaping SAR ADC as the quantizer,which requires only a single OTA to realize the third-order noise-shaping.The ADC's shaping capability is further strengthened,the complexity of loop filter is reduced,and the PVT robustness is improved.The proposed hybrid ADC combines the merits of continuoustime and discrete-time ?? ADCs.It is low-power,high-resolution,PVT-stable and has the anti-aliasing filtering capability,making it suitable for wireless communication systems.Fabricated in 40 nm CMOS process,the third-order continuous-time ?? ADC measures 70 d B signal-to-noise-and-distortion ratio(SNDR)and 12.5 MHz bandwidth with 500 MHz sampling frequency and 20 × OSR.The total power is 1.16 m W,the chip area is 0.029 mm~2.3.We propose a new MES method which can efficiently address the mismatch issue in high-resolution ADCs,and has low complexity and high flexibility.Comparing to the classic dynamic element matching(DEM)technique whose complexity increases exponentially with number of bits,the complexity of the proposed EF MES only increases linearly with ADC's resolution.Thus,it significantly reduces the chip area and power,and is suitable for high-resolution applications.Comparing to the prior first-order EF MES,the proposed one can achieve the aggressive second-order shaping and can extend to various high-order MES,making it generally applicable for low-pass,band-pass and high-pass ADCs.Besides,we propose to use digital prediction to address the dynamic range loss problem.The works of this dissertation achieve a breakthrough in the key techniques of energyefficient ADC design,provide several feasible solutions for low-power and high-resolution ADC in the advanced CMOS technology.These works are helpful in the development of high-resolution and energy-efficient ADC techniques,they can find wide applications in IOT and wireless communication systems.