Research And Implementation Of Successive-Approximation Register Analog-to-Digital Converter And Its Noise-Shaping Hybrid Architecture

Analog-to-digital converter(ADC)which is the interface of real physical world and digital domain,is extensively used for aerospace,radars,communications,mea-surements and medical examinations.In the era of information,the ever-growing need of information processing capability requires the ADCs to work at higher and higher performance.As the IC process scaled down,transistors are getting faster working speed.Meanwhile,the I/V characteristics,gain,supply voltage,process variations and leak current performance of transistor has degenerated.These factors deterio-rate the performance of analog circuits and increase the difficulty of designing high-performance ADCs.In addition,compared to the rapid development of integrated cir-cuits,the progress of battery technology and chip cooling technology is relatively slow.The power consumption of ADCs rises rapidly with the increase of conversion rate,which heats up the chips and leads to performance degradation.Therefore,it is also an important issue to reduce the power consumption in ADC design.In various ADC topologies,the successive-approximation-register(SAR)ADC has very little analog circuity,which makes it superior on low-voltage,low-power,high-speed advanced processes.Meanwhile,as the application requirements keep growing,traditional ADC topologies show limitations of overall performance.In recent years,researchers are trying to reconstruct hybrid ADC architectures which combine the ad-vantages of several conventional techniques.SAR ADCs are suitable to be utilized in hybrid architectures to achieve high performance with low power consumption,as they have high energy efficiency,small area,and flexible structure.This dissertation stud-ies the conversion time and power consumption of SAR ADCs,and discusses how to design high-performance and low-power SAR ADC IP cores.Furthermore,the over-sampling and noise shaping techniques are introduced into the SAR ADC to realize a high-precision low-power hybrid ADC.The main work and innovation of this disserta-tion are as follows:(1)The size and power consumption of digital circuits in SAR ADCs increases dramatically as resolution and sampling rate goes up.To solve this problem,this dis-sertation analyzes the power consumption and delay mechanisms of the successive-approximation logic of a typical asynchronous SAR ADC,and provides strategies to reduce both of them.Following these strategies,a unique direct-pass SA logic is pro-posed.The timing sequence is optimized,and the unnecessary internal switching power of the typical dynamic logic is avoided.Besides,a serial-comparator architecture and a comparator meta-stability protection circuit are proposed to further enhance the speed and reduce the power consumption.A prototype 10-bit SAR ADC based on the pro-posed techniques is fabricated in 130 nm CMOS.It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate,and has a total power consumption of 555?W,while the digital part consumes only 203 ?W.(2)In order to improve the conversion speed of single-channel SAR ADCs,the tim-ing redundancy in several typical asynchronous SAR ADC architectures is analyzed.A speed-enhancing dual-trial instantaneous switching architecture for SAR ADCs is presented.The proposed architecture uses two capacitive digital-to-analog converter arrays to generate two possible outputs while the comparator is in the regeneration pro-cess.Such an approach allows the overlapping of the DAC settling,the comparator reset,and the comparator regeneration,which significantly improves the conversion speed.Furthermore,the random nature of the internal channel selection converts the mismatches between both channels into wideband noise,which improves the spurious-free dynamic range.An 8-bit ADC based on the proposed architecture is simulated in 130 nm CMOS,which achieves 360 MS/s sampling rate with 1.2 V supply.(3)For effective resolutions beyond 10 bits,it is difficult to fulfill the compara-tor noise and digital-to-analog converter noise requirement with reasonable area and power consumption in SAR ADCs.The oversampling and noise-shaping characteris-tics of sigma-delta modulators can be employed in SAR ADCs to achieve higher res-olution.The conventional noise-shaping technique is based on an operational ampli-fier which has low power-efficiency and is difficult to design in advanced processes.Passive noise-shaping techniques are introduced into the SAR ADC.However,clock and circuit complexity is shown in the existing designs.This dissertation presents an opamp-free solution to implement noise-shaping technique in SAR ADCs.With de-layed quantization error applied to both comparator and sample-hold circuit through dual feedback paths,effective noise-shaping is achieved using a passive loop filter.A SAR ADC adopting the proposed opamp-free noise-shaping solution is designed in a 0.18-?m CMOS process.The measurement result exhibits 10.0-bit accuracy at 40 MS/s sampling frequency based on 8-bit DAC when the oversampling rate is 4.