Research On High Level Models And Circuit Technologies Of Noise Shaping Successive Approximation Register Analog-to-Digital Converter

It is well known that data converters work at the interface of the analog and digital world,so analog-to-digital converter(ADC)plays a very important role in the electronic world.With the development of science and technology and CMOS process,ADC performance requirements in various application fields are becoming higher and higher,especially in advanced fields such as biological,medical electronics and portable handheld electronic devices,which not only require ADC to have high resolution,but also lower power consumption.The traditional ADC with a single structure can no longer meet the needs of the system,and the research on a new ADC with a mixed structure is extremely urgent.Noise shaping SAR ADC is a new hybrid ADC combining sigma-delta ADC and SAR ADC.It combines sigma-delta ADC noise shaping and oversamping while preserving the SAR ADC's advantage of low power consumption.Firstly,the whole structure and basic principle of noise shaping SAR ADC are introduced.As an important module of SAR ADC,this thesis studies the core circuit of SAR ADC,including sampling switch,DAC switch timing,comparator and SAR control logic.Then,the thesis uses MATLAB to conduct system modeling and zero point optimization for noise shaping SAR ADC,and analyzes and simulates the influence of non-ideal factors on the system,including clock jitter,switching thermal noise,offset voltage of comparator,noise of comparator and DAC mismatch error,so as to improve its noise shaping performance.On this basis,the paper designed a dynamic amplifier based error feedback(EF)third-order passive noise shaping SAR ADC.Cross-coupling cascode dynamic amplifier is used to amplify the quantized residual difference,compared with the traditional single-stage dynamic amplifier,its gain is obviously improved.And finite impulse response(FIR)filter is used for loop filtering,which avoid the use of active operational amplifier and reduce the power consumption of the circuit.What's more,a 9-bit VCM-based switch timing SAR ADC was used for signal quantization.For the capacitance mismatch error in DAC array,this thesis adopts the method of capacitance mismatch error shaping(MES)to solve it.Compared with the classical calibration and dynamic element matching(DEM)techneque,its circuit complexity and hardware consumption are greatly reduced.The circuit is simulated in SMIC 0.18?m CMOS process and achieves an ENOB of 12.8 bit with a signal bandwidth of 125 KHz and a sampling clock of 2 MS/s at an oversampling ratio of 8.It consumes 105?W from a 1.8 V power supply,and the core area is 680×780?m2.