A Research Of Novel Incremental Noise-shaping Successive Approximation Register Analog-to-Digital Converter

With the development of Internet of Thing(Io T)technology,more and more intelligent terminal devices have entered the market.In order to ensure the long-term use and convenient carrying of the device,the chip is required to meet the two requirements of low power consumption and small area.As a bridge connecting the analog world and the digital one,the research of Analog-to-Digital Converter(ADC)is very important,and the ADC applied to the Io T needs to meet the needs of low power consumption and small area.In recent years,due to the development of technology,noise-shaping(NS)successive approximation register(SAR)ADC has become a research hotspot because of its simple circuit structure,achieving small area and high power consumption efficiency.At present.The accuracy of the NS SAR ADC is not high,and the Signal-to-Noise Ratio(SNR)is difficult to reach more than 80d B.Incremental Sigma-Delta ADC is a kind of ultra-high resolution oversampling ADC structure.Because of its high Over-Sampling Ratio(OSR)and reset signal,it can often achieve high resolution on the low precision quantizer,but the input bandwidth will be very limited.In this paper,we try to study the structure of NS SAR ADC,keep the advantages of low power consumption of SAR ADC,and combine it with Increment Sigma-Delta ADC to achieve a higher SNR at a lower OSR.The main contents and innovations of this paper are as follows:(1)a novel Incremental Noise-Shaping SAR ADC is proposed in the ADC scheme,which uses the Error-Feedback(EF)system to delay the residue voltage and realizes the 2^nd noise shaping modulation.(2)A dynamic amplifier with gain error calibration is proposed,which can realize the 2^nd noise shaping(1-z^-1)² and improve the SNR on the premise of not over increasing the power consumption.(3)In order to reduce the influence of the Digital-to-Analog Converter(DAC)capacitance mismatch system,a new dynamic element matching calibration method is proposed in this paper,which makes it more suitable for NS SAR ADC.This paper is based on TSMC 28nm HPC process,which power supply voltage is1V.6-bits differential capacitor structure is adopted and the sampling frequency is128MS/s with 64 OSR.The circuit simulation results show that SNDR can reach89.2d B and the Effective Number of Bits(ENOB)is 14.52.ADC core chip area is300×200?m² which power consumption is only 1.96m W,and the final Schreier FoM is 176.2dB.