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Design Of High Precision Noise Shaping SAR ADC

Posted on:2022-08-19Degree:MasterType:Thesis
Country:ChinaCandidate:C J LvFull Text:PDF
GTID:2518306509495584Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
With the continuous development of digital processing terminals,various electronic products have increased the accuracy,speed,reliability and other performance requirements of ADC(Analog-to-Digital Converter)from generation to generation,and the performance of the traditional single ADC architecture is difficult to meet.In recent years,ADCs with hybrid structures have integrated the advantages of different architectures to improve the performance of ADCs and become a research hotspot.The traditional successive approximation analog-to-digital converter has a simple function implementation method,low power consumption,and a small layout area,but it is difficult to achieve high precision(above 14 bits)without a calibration algorithm.The Sigma-Delta ADC is a high-precision ADC,but its disadvantages are high power consumption and slow speed.Therefore,combining the two,by selecting an appropriate oversampling rate and Sigma-Delta modulator(SDM),and using an appropriate amount of bandwidth reduction in exchange for higher ADC accuracy,can finally achieve the goal of having the advantages of both ADCs.This article applies the noise shaping technology of Sigma-Delta ADC to SAR ADC,and realizes a NS SAR(Noise Shaping Successive-Approximation-Register,noise shaping successive approximation type)ADC.Compared with the traditional architecture,the architecture proposed in this article not only has the high speed and low power consumption of SAR ADC,but also can achieve high precision.On this basis,the comparator is improved to a four-input,and a cascaded integrator feedforward structure loop is adopted.A Sigma-Delta modulator composed of a filter and an active integrator can achieve a better noise shaping effect and realize a 14 bit NS SAR ADC.Based on the Cadence platform,this paper uses SMIC 1P6 M 0.18?W technology to simulate and verify the overall circuit.The sampling rate is 2MS/s,the performance of the NS SAR ADC is ENOB=13.72 bit,SNR=82.36 d B,and SFDR=93.10 d B.The power consumption of the analog circuit part is 1.68 m W,and the power consumption of the digital circuit part is0.95 mW.
Keywords/Search Tags:Successive approximation analog-to-digital converter, Sigma-Delta modulator, Oversampling, Noise shaping
PDF Full Text Request
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