The Research And Design Of Dual-mode Fractional-N Pll Applied In Navigation Receiver

Satellite navigation and positioning system is a radio navigation system using artificial earth satellite as navigation station.It plays an extremely important role in national economic construction,military and national defense fields.Ground receiving terminal is a user-side device used to receive satellite navigation signals,process the signals with algorithms and analyze the positioning coordinates.For receiving terminal,PLL is one of the most important modules.Its performance is closely related to the performance of the RF front-end chip of the navigation receiver.This paper focuses on the design of dual-mode fractional-N PLL in navigation receiver.Firstly,the composition of the fractional-N PLL,the working principle of each module and the main performance indicators are introduced.The system transfer function of PLL is deduced,the linearized model is established,and the system parameters of PLL are designed.The system parameters are substituted for the stability simulation in MATLAB,and the behavior level simulation is carried out by using Simulink model.Based on the phase noise linear transmission model of PLL,the equivalent output phase noise of each module is obtained by Laplace transform.The output phase noise curve of the PLL system is obtained by fitting the noise sources with MATLAB,which can guide the design of the module circuit.Based on the analysis and design of PLL system,the implementation of specific circuits is started.The"dead zone"and"blind zone"effects of the phase discriminator,as well as the non-ideal effects of charge leakage,current mismatch,charge injection,clock feedthrough and charge sharing of the charge pump are analyzed in detail.The structure selection and design principle of voltage controlled oscillator(VCO),the design method of the divided by 2 divider,the realization of programmable divider,the noise shaping of the sigma delta modulator,the principle,structure and algorithm description of the automatic frequency correction circuit are described.According to the theoretical analysis to guide the design of the circuit,and use Cadence Spectre,MATLAB,Spectre Verilog-AMS and other simulation software to verify one by one.GSMC 0.13?m 1P7M CMOS technology is used for circuit design and layout drawing.The chip area of the PLL is 4.06 x 0.91 mm~2.The layout of sigma-delta modulator and automatic frequency correction circuit is semi-customized design method,and the layout of other modules is fully customized design method.The test PCB of the chip is designed by using Or CAD Capture tool of Cadence Company,and the navigation receiver chip after tape-out is tested.The test results show that the PLL can work normally at 1.2V supply voltage.The frequency tuning range of 1.2GHz PLL is from 0.96GHz to 1.38GHz.The in-band noise is-88d Bc/Hz@10KHz,the out-band noise is-93d Bc/Hz@100KHz,-117d Bc/Hz@1MHz,and the RMS jitter from 10KHz to 1MHz is 0.3ps.The frequency tuning range of 1.5GHz PLL is from 1.13GHz to 1.71GHz.The in-band noise is-87d Bc/Hz@10KHz,the out-band noise is-92d Bc/Hz@100KHz,-115d Bc/Hz@1MHz,and the RMSjitter from10KHz to 1MHz is 0.5ps.It meets the performance requirements of navigation receiver.