Clock Source For The Applications Of Satellite Navigation Receiver And Analog-to-digital Converter Chip Design

Phase-locked loop (PLL) is a circuit which can synchronize its output signal with an input reference signal in frequency and phase. It's a fundamental and very important module in analog and mixed-signal integrated circuits. Because of its ability of tracking,acquisition and operating as a narrow-band filter, PLL is widely used in many fields such as astronautics, communication, microprocessor, and so on. One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor. With the development of integrated circuits and the emergence of SOC (System on a Chip) technology, PLL has played so important a role in VLSI circuits and analog integrated circuits that it is worth researching and esigning.Analog-to-digital (ADC) converter is the key device of advanced communication rada acoustic susceptance and many consume eletronics .As a special interface connects with analog and digital circuits, high performance analog-to-digital converter is more and more important in whole system design. Now the development of the technology has more need of the performance of the ADC,especially the speed. It even has become the key factor of the device performance.In the basic of the analyzing of PLL and ADC's basic principle and typical schematics,this paper designs a 50MHz clock generator and a 2bits ADC.the sampling clock of ADC is the output clock of PLL.we analysis the principle of PLL and ADC detailly,and we construct a timimg model of PLL clock generator in SIMULINK to check whether the parameter of PLL is right.then the schematics of PLL and ADC are designed in cadence environment with JAZZ 0.35um BiCMOS process;the layouts of PLL and ADC are designed with Virtuoso Layout XL.we use the spectre tool to simulate the design.the results show that the performance of design is well.Finally,all works are completed.