The Design Of Mixed Analog-digital Phase-locked Loop In Serial RapidIO

Serial RapidIO is a newly-emerged high-speed interconnect protocol which has drawn wide attention with its excellent performance in data transfer. But in China, research on it is still at an initial stage. In most cases we rely on the direct use of IP core or chip.Phase-Locked Loop (PLL), which serves as a clock generator, is an integral part of the RapidIO system. Therefore, it is critical to develop a PLL that meets the needs of the project in order to have a breakthrough in the RapidIO technology. In this paper, a pump-based PLL with digital-analog hybrid design was designed using 0.13μm CMOS process, so as to meet the needs of the serial RapidIO interface chip design. The PLL can generate three kinds of output frequency, namely 1.25GHz, 2.5GHz and 3.125GHz, which can meet the requirements of SRIO protocol version 1.3. The major highlights of the research are as follows:1. In accordance with the design requirements of the PLL, the paper designs modules of the PLL. It pointed out the module circuit design problems, and targeted for the design optimization.2. A charge pump circuit with simple structure which not only eliminates the usual problem of charge-pump circuit voltage hopping but won't increase power dissipation was designed in the paper.3. A duplex structure ring-shaped voltage-controlled oscillators, whose main body included only 8 inverters with simple but excellent oscillation circuit was designed in the paper so as to meet the design requirements for higher frequency. Through Hspice simulation, it is verified that the PLL can achieve the oscillation frequency of 5GHz and above on 1.2V.4. The paper makes a digital-analog hybrid PLL circuit and carried out DRC, ERC, LVS assessment building on this. The Hspice simulation at the circuit-level and layout-level were also carried out.