Research And Design Of Low Phase Noise Fractional-N Phase Locked Loop

With the fast development of the electronic market,people's demand for smart devices is burgeoning.The burgeoning 5G mobile phone attracts many users because of its fast data sending and receiving speed.Data communication network has entered thousands of households.To meet the needs of users,providing high-quality communication transmission network has brought some challenges to designers.Among them,PLL is one of the key modules of the communication transfer system,which can contrast the input reference signal with the output feedback signal,and finally output a stable base frequency signal.Based on the application environment of high-speed serial communication transmission system and the needs of users,this paper focuses on a PLL with low phase noise,high precision and stable output.First of all,the basic structure of PLL circuit is introduced,the working principle of system and sub-modules is described,and the performance index of PLL is discussed.PLL is studied and analyzed from the system level.By comparing the S-domain linear model and equivalent phase noise model of CPPLL and SSPLL,the reliability and dynamic characteristics of the two types of phase-locked loop are analyzed,and SSPLL has lower phase noise.The behavior-level model is established by Verilog-A language,which verifies the above theoretical analysis.Based on the basic structure of sub-sampling,the system architecture is optimized,and the digital time converter and Sigma-Delta modulator are used to realize the fractional frequency division function of PLL and improve the frequency division accuracy.The digital time converter controls the delay of the input signal,adjusts the sampling timing,and uses Sigma-Delta modulation technology to compensate for the fractional spurious generated by frequency division,which plays a role in reducing the phase noise of PLL.Later,design and optimize the sub-modules.In order to shorten the locking time,the dead zone module with adjustable delay is added to PFD of the frequency acquisition loop.In order to further optimize the phase noise performance,the voltage-controlled oscillator adopts capacitor inductor type voltage-controlled oscillator,and at the same time,a switched capacitor array is added to expand the output frequency range and improve the tuning range The parameter values of the loop filter are designed by combining Matlab software with theoretical derivation.Then,a mixed simulation environment of digital and analog is built,and the transient simulation analysis of the whole PLL is carried out.The phase noise performance of PLL system is analyzed by using Cadence spectre RF and Hspice software and combining the phase noise performance of each sub-module.Finally,aiming at the designed circuit,the layout design is completed on the premise of fully considering the device matching and noise isolation ability,and it is verified by simulation.Based on TSMC 130 nm process,a fractional-N sub-sampling phase-locked loop circuit with low phase noise performance is designed in this paper.When the working voltage of the PLL is1.8V and the input reference signal frequency is 62.5MHz,the system output frequency ranges from 2.2 GHz to 2.8 GHz.When the output frequency is 2.5GHz,the lock time is 1.7(?)s,the power consumption is 28.04 m W,and the phase noise is-112 d Bc/Hz at 1MHz frequency offset.The design achieves the expected goal.