Research&Design Of The Low-Power Dual-mode Fractional-N PLL

With the rapid development of wireless communication systems, as well as the progressive realization of intelligent life and Internet of things, research and development of the frequency synthesizers based on the structure of PLLs has always been a central issue. The shrinking of CMOS process geometries and the universalization of portable devices require integrated circuits to work with low voltage and low power consumption. And the increasingly crowded communication bands need the phase-locked loops with a higher frequency resolution, which makes the traditional integer-divider PLLs gradually being replaced by fractional-N. What’s more, multi-mode multi-standard system platforms need the PLLs to be able to have wideband outputs or multi-mode outputs. With2.4GHz and5.8GHz becoming the public frequencies of wireless communications,3.6GHz also has been newly added to the public frequencies in recent years. Therefore, this thesis studies and designs a low-power2.4/3.6GHz dual-mode fractional-N PLL, corresponding to the domestic rapid development of wireless communication systems, and we hope this thesis could play an important role in the domestic independent R&D of high-end general chips and development of the integrated circuit industry.The main work and innovations include:1. Based on the basic theory and the linear model analysis of each module in PLL system, the system transmission model and noise transmission model of fractional-N PLL are established. The third-order loop filter in this design is analyzed and the device parameters are deduced, to determine the loop bandwidth and phase margin. The loop characteristics of PLL and the noise transfer characteristics of each module are simulated, and the effects which are made by the noise of each module on the output signal are deduced, so that to provide guidance for PLL design and optimization.2. Analyze the "dead zone" and "blind zone" problems of PFD, the non-ideal effects and structure selection of CP, the phase noise theory and design principles of VCO, the speed and power trade-off consideration of prescaler, the implementation strategies of fractional divider, the noise shaping effect of S-A modulator, and the main performance options of AFC. The high-performance circuit structures and algorithms complying with the design specifications are proposed, and the feature and performance simulations are validated. Loop stability design and the suppression of reference spurs are also discussed. In addition, the test results show that the AFC can’t work properly, so the improvement is carried out, making the accuracy and speed of AFC better.3. Using domestic40nm1P8M Mixed-signal CMOS process, a2.4/3.6GHz dual-mode fractional-N PLL is implemented. The overall simulation meets the design specifications, and the PCB for chip testing is designed. However, due to the first-time taping-out, the process model deviation can’t be grasped, which causes the deviation of PLL output frequency between test and design, and relatively high output reference spurs (generally less than-50dBc). These problems will be adjusted in the next version. The test results show that this chip can work at0.8V supply voltage (VCO at0.5V). In the2.4GHz mode, the PLL tuning range is2.814-3.404GHz. The phase noise is-122.5dBc/Hz@1MHz. The reference spurs are lower than-38dBc. The power consumption is5.3mW. The locking time is less than20us. And the FOM is-185. In3.6GHz mode, the PLL tuning range is4.093-4.933GHz. The phase noise is-115dBc/Hz@1MHz. The reference spurs are lower than-44.5dBc. The power consumption is5.9mW. The locking time is less than20μs. And the FOM is-180. In both2.4and3.6GHz modes, the FOMs are at the advanced level compared with the existing researches of PLL at home and abroad.Main innovations:Improvements of low voltage, low current mismatch CP and AFC algorithm design. Implementation of2.4/3.6GHz dual-mode VCO and fractional-N PLL.