The Study And Design Of2.5GHz CMOS Phase-locked Loop

High speed phase-locked loop circuits as an important component of clock recovery circuit and frequency synthesizer circuit are widely used in modem optical fiber communication and wireless communication. This article focuses on PLL (Phase-Locked Loop, PLL) circuit design and realization in2.5Gbps serial transceivers. The subject came from the National863Program:"The Development of Core Chip in Broad Band Switch" and the Shaanxi Significant Science and Technology Project:"The Development of2.5Gb/s Serial Transceiver Chip and Its IP Core". In this dissertation, theory, model, circuit design and simulation of charge pump phase locked loop are studied.This thesis focuses on circuit design and implementation of a2.5Ghz mixed-signal charge pump PLL (phase-locked loop). The mathematical and noise models of PLL were established based on the precious theoretical analysis and the specification, draft and parameters of the PLL were presented and discussed in detail in the paper. With considering maximum power and jitter of the PLL, a circuit of the PLL was implemented in SMIC0.18μm CMOS Technology and was verified by Spectre simulation environment. The results of simulation show that all performance of the PLL has achieved the design requirements completely which are40mW power consumption,21ps peak-to-peak jitter of output clock and-105dBc/Hz SSB(Single Side-Band) phase noise at a5MHz offset.