Design Of COMS Phase-locked Loop Applied For Navigation Receiver

Phase-locked loops(PLL) have been widely applied in both communication systems and information processing systems. In wireless transmission systems, PLLs generate local oscillations, modulate and demodulate signals. In cable communication systems, PLL is a vital parts of CDR(Clock Data Recovery) circuit. In digital systems, the quality of clock sig nal generated by PLL influences the performance of the whole system.A low-phase-noise charge pump PLL, which out puts a signal near 1.2GHz with a 62 MHz reference input signal, is designed and simulated. The PLL, designed to generate local oscillation signa l for RF front-end of satellite navigation receiver, can realize integrate frequency division with a ratio of 20 and can realize fractional frequency division after connecting a peripheral division ratio controller.The design of the CMOS charge pump PLL is completed in two aspects. The first aspect is the architecture choice and circuits design of charge pump PLL modules, including PFD, charge pump, VCO and divider. The content includes: cancellation of unideal affects, optimization of phase noise, trans fer function derivation and chose of modules. The second aspect is the loop module and optimization. Assuming that PLL is a linear time-invariant system, PLL can be modulated by transfer function generated after Laplace conversion. The loop parameters, as well as module circuits, can be optimized according to the simulation results of MATLAB program which calculates the contributions of individual modules to the output phase noise via phase noise transfer function.The circuit and layout of CMOS charge pump PLL are designed and simulated in SMIC 180 nm procession on Cadence platform. It can synthesize the wanted frequency and can accomplish program targets, according to the simulation results.