Gigbit High Speed Serial Interface IC's System Design & Some Key Technologies Research

The state of art CPU could run its core at more than 3GHz, and CPU front system bus at 1GHz (bandwidth 8GB/s).This makes I/O interface a bottleneck of high performance systems, especially graphics and disk storage. Increase the bandwidth of an I/O bus may be achieved by either increase bus width (e.g. 16b to 32b) or by increasing operating frequency. Parallel interface is difficult to be implemented because of its nature drawback, e.g. clock skew. Technologies such as embedded clock, point-to-point linkage, low voltage differential signal transmission and data encoding, enables gigabit serial bus get reliable high transfer rate at practical long distance, and become the next generation of interconnection interfaces. To meet different sub-system connection, the computer industry develops several gigabit serial interface specifications, e.g. SATA, PCI-Express.Gigabit serial interface integrated circuits play an important role in high speed serial I/O bus. At gigabit transition rate, gigabit integrated circuits usually use analog circuits to perform gigabit rate functions such as clock generator and clock data recovery circuit. Compared to digital circuit, analog circuit has a lower noise tolerance, needs more area and power consumption, is more sensitive with process change and has a lower testability. Additionally, integrating a large amount of analog circuit in a digital system is very difficult.Because digital circuit has many advantages over analog circuit, it is becoming a technical trend to implement digital circuits to replace as many analog circuits as possible. The thesis describes a phase digital sampling principle to implement the most critical functions in a gigabit serial interface system: system clock generator,high speed transmission clock generator and high speed serial clock data recovery circuit.Circuits using digital phase analysis principle have been implemented by a digital standard cell circuit plus front low voltage differential IO cells, and are fabricated by 0.18um CMOS process technology. Compared to analog circuit, digital circuit design is more easily portable and has more simple digital process, less area and power consumption.In addition, thesis discusses a high speed serial interface system IC design on layered protocol model. A system architecture model with an embedded MCU achieves not only flexibility and also scalability.