Design Of1.2Gbps CMOS Clock And Data Recovery Circuit For The Serial Communication

In modern high speed data transmission field, serial connection communicationsystem has been gradually replaced the parallel connection communication system.Because of the rapid development of serial connection communication technology,the Clock and Data Recovery circuit (CDR) which is one part of serial connectioncommunication system gets more and more attention. The performance of the CDRcircuit, as the core component of serial communication system, directly affectsaccuracy of the output data at the receiving end.Based on the comprehensive literature research，a dual phase-locked-loop (PLL)based CDR is adopted, after analyzing this architecture in detail, and in allusion tothe drawback of second harmonic lock of the adopted CDR circuit, a new topologyof CDR circuit with an automatic monitor and an second-harmonic-lock-cancelcircuit is proposed. In order to verify the correctness of the proposed CDR circuit,the Verilog-A language was used to set up the Behavioral Model of the proposedCDR circuit, while the simulation results confirms the correctness of the proposedCDR circuit.After verification of the behavioral level model, the proposed CDR circuit andthe corresponding layout has been implemented in SMIC0.18CMOS process, whilethe simulation results which is with an215-1pseudorandom bit sequence (PRBS)input data show that the time of the clock and data recovery process is200ns, whilethe peak-to-peak jitter of the recovered data and clock are21.33ps and19.8psrespectively, with the differential swing of the recovered clock and data being700mV, and the static power consumption of the CDR is97mW with a1.8V powersupply. The post simulation shows that the recovering time turns to300ns, while thepeak-to-peak jitter of the recovered clock and data change to66.57ps and73.83psrespectively, with the same output swing. The total area of the CDR layout is658μm×643μm.