Design Of Clock Data Recovery Circuit In High Speed Serial Interface

The arrival of the information society has brought new challenges to the data transmission interface.High-speed information exchange necessarily requires the transmission interface to exchange a large amount of data in a short time.Traditional parallel interfaces have emerged some significant shortcomings as data rates continue to increase.The transmission of synchronous clocks requires not only the use of additional channel resources but also severe crosstalk between high-speed data.In this case,the serial interface stands out and solves many problems such as clock skew and signal crosstalk.However,when the data rate is too high to ignore the effects of the parasitic parameters of the interface itself,the serial interface transmission speed also reaches the bottleneck.The high-speed serial interface that pre-processes the input data by adding a clock data recovery circuit to the interface gradually replaces the ordinary serial interface,which is the mainstream of the new era,such as the most used USB and PCI-E interfaces.In this thesis,a clock data recovery circuit suitable for high-speed serial interface is designed by GF0.18?m ULL CMOS process.The dual-loop clock data recovery circuit based on Phase Lock Loop(PLL)not only does not require an additional reference clock,which reduces the use cost of the high-speed serial interface,and the dual-loop structure effectively solves the contradictory between phase noise and the locking speed.The half-rate phase detector operating in the double-edge sampling mode can accurately identify the phase difference between the half-rate clock and the input data,reduces the operating frequency of the overall circuit,and greatly reduces the power consumption of the circuit.The half-rate digital auto-phasing discriminator can capture the frequency difference between the local clock and the input data in time,increasing the frequency capture range of the entire loop.The four-stage differential ring voltage controlled oscillator not only has the advantages of high integration and large frequency adjustment range,but also directly provides four clock signals with a phase difference of 45° required by the discriminator.The charge pump design uses a fully differential architecture with a differential voltage controlled oscillator and a third-order passive loop filter to suppress the effects of ambient noise on the recovered data.The overall circuit design process is divided into three stages: Simulink modeling,noise analysis and transistor-level circuit design.Among them,the Simulink modeling stage obtains appropriate loop parameters by systematically modeling and analyzing the loop and each module;the noise analysis stage mainly analyzes the noise source based on the Lesson and the Razavi model from the theoretical persepctive,and guides the circuit design;the transistor-level circuit design phase uses the EDA tools such as Virtuoso and Spectre for circuit schematic and layout design and simulation.The simulation results show that the circuit can recover 2.5Gbps pseudo-random data and 1.25 GHz local sampling clock stably under the condition of 1.8V power supply.The jitter of the output data is approximately 23 ps,and the phase noise of the output clock is-112.3dBc/Hz@1MHz.The overall circuit power consumption is about 158 mW,and the layout area is 460?m×530?m.