The Design Of The Integrated CP PLL With Capacitance Multiplier Technology

Narrowband Internet of Things(NB-Io T)communication standard puts forward low-cost and low-power design requirements for RF transceivers.The frequency synthesizer is one of the key modules that affect the performance and cost of RF transceivers.A 900 MHz fully integrated charge pump phase-locked loop is designed to satisfy the needs of NB-Io T standard.In this paper,the transfer function of each sub-module in PLL is established.The loop parameters are solved by the Phase Margin Maximum Method which can guarantee the stability of the loop.In the part of circuit implementation,each sub-circuits are optimized to meet the requirements of low-cost and low-phase noise.The fully differential architecture and the Latch circuit are adopted in the phase-frequency detector design which accurately aligns the differential ends.The current steering charge pump and bootstrap structure are used in charge pump design,which can eliminate the charge sharing and improve the charge pump matching.In the design of the loop filter,two different capacitor multiply circuit,the capacitor multiply structure based on the current mirror and the capacitor multiply structure based on the unity gain amplifier are analyzed both.The latter has better noise performance.Compared with the passive loop filter,the layout area is reduced by 64% after adopting the capacitor multiply circuit.LC voltage-controlled oscillator architecture is adopted in VCO,using 3bit switch capacitor to increase the tuning range.TSPC structure flip-flop and logic gate structure flip-flop are respectively adopted in different working frequency to take account of the noise and power consumption.This paper also analyzes of noise from each sub-module and deduces the transfer function,which pointing out the direction for optimizing the noise performance.A 900 MHz fully integrated charge pump phase-locked loop is implemented in TSMC 90 nm Mixed-Signal CMOS process.According to the simulation result,the PLL which adopted passive filter achieve 5us lock time.The value of phase noise is-116 dBc/Hz@1MHz.The test result shows the value of phase noise is-110.62 dBc/Hz@1MHz.The reference spur is-59.636 dBc.The PLL which adopted capacitor multiply circuit achieve 20 us lock time.The value of phase noise is-114 dBc/Hz @1MHz.