Based On Noise Analysis Of The Charge Pump Phase-locked Loop Design

Phase-Locked Loops (PLL) is a fundamental and very important building block in analog and mixed-signal integrated circuits. Phase-locked system can track the input signal phase and frequency, output phase-locked and low jitter other frequency signals. In most system application, PLLs server as a powerful technical course to afford perfect resolve method. But PLLs design process involves much theory and application base, such as signal and system, integrated electronics, layout, semiconductor technology, measurement etc. So, it's very necessary to deeply research the principle of phase-locked system, capture the design and analysis method, set up IP library and afford ready design block for system.The research of this project is concentrated on PLLs phase noise. It aimed at discovery some special difficulty in implementing phase-locked system.The project begins from describing the principles of phase-locked system with emphasis on monolithic implementations. Following a detail analysis from the PLLs system to module based on signal and system, we especially develop some important characters: the loop dynamics in locked state, tracking behavior, acquisition time, higher order loops and phase noise. Meanwhile, we simply introduce the principle of Delay-Locked Loops (DLLs). Next, we detailed illustrate the Charge-Pump PLLs (CPLLs) design process, including module configuration, simulation thought and analysis. Next, we compare the measure results with the simulation and correct the fault in design. Finally, we analyze the DLLs in waveform-shaping circuit, but only give out the circuit work principle and simulation result.The main contributions and creative points of this dissertation are as follow:1. It proposes a better voltage-controlled ring oscillator, which has following advantages: high linear VCO gain, high maxim output frequency, high power-supply rejection ratio, low noise, low output signal jitter, easy integrated etc.2. It proposes a method that can eliminate the phase/frequency detector's "dead zone".3. It proposes a method that can give precise delay-time to Tl waveform-shaping based on the principle of DLLs.This dissertation is partially supported by Mixed-signal Group, ASIC. Huawei Techology Co., Ltd. The research produce has been used in produce and fulfill the requirements.