Design Of A Charge Pump Phase-Locked Loop For Frequency Synthesizer

These years, as the techniques such as computer, radar, navigation, especially the wireless communication technology develop rapidly, CMOS single-chip radio frequency transceiver is widely implemented for its advantages of low cost, low power consumption, and high integration. The frequency synthesizer is the critical part of the transceiver, because it could meet the high requirement for the frequency stability, spectrum purity, frequency range and the number of output frequencies. Frequency synthesizer, based on the Phase-Locked Loop techniques, could generate frequencies from single or multiple frequencies. This thesis carries out research on the theory, model and design methods of Charge-Pump Phase-Locked Loop (CPPLL), with the objective to design a frequency synthesizer later.Based on the basic linear model of the Phase-Locked Loop, chapter 2 establishes the high-order model of the CPPLL and analysis the stability of the high-order loop. Apart from the linear model, this chapter establishes the noise model of the CPPLL, on the basis of which lower-level circuits are designed and optimized on the latter chapters. The detailed working principles of the PLL modules are introduced then. Comparison among different ways to design Phase Frequency Detector (PFD) is made, and the circuit is optimized to resolve the contradiction of delay span required by the "Dead Zone" effect and working frequency. Also, various kinds of Charge Pump (CP) are compared by their performance on the none-ideal effects, including current matching, clock feeding-through, charge sharing, etc.The fourth chapter focuses on a specific design of CPPLL with the 0.18um process. Following the top-down design flow, design task is carried out from making design specification to doing transistor-level design. The PFD designed eliminates the "Dead Zone" effect and achieves a good detecting precision and a high working frequency. The high-level charge pump designed shows a perfect current matching performance, based on the error operational amplifier technique. According to the system model established before, a three-order loop filter optimized for its parameter, which is able to eliminate the high-order harmonic wave.In the final part, the thesis studies and designs the layout of a CPPLL. First, some design principles are listed about the analog circuit layout and the mixed-signal circuit layout. Next, the source of the noise and disturbance in the mixed-signal layout is analyzed and the corresponding resolution is proposed. Finally, under the guidelines of the layout theory, the layout of the CPPLL modules is completed and optimized with the disturbance-reducing methods discussed before. It achieves a tightly-arranged layout with less-disturbance.