Design Of Phase Locked Loop Circuit And Analysis Of Phase Noise

This paper is focused on the design of a Charge Pump PLL (Phase Locked Loop)and the researching of PLL's phase noise characteristic, and then the PLL circuit issimulated in detail. The charge pump PLL is mainly used for clock generator modulein MCU, whose output clock signal is 50% duty cycle, output frequency of 128MHzand maximum output frequency is 192MHz. These specifications can meet therequirements of high speed MCU integrated circuits.The design method of Top to Down is used, which is from the system leveldesign of charge pump PLL to the transistor level design of each block in PLL. Firstly,the mathematic model of PLL is built by Matlab and the behavior model is built byVerilogA language. Then the loop parameters are optimized by these models.Secondly, after each block's specification is decided, detailed design and simulation ofthese blocks are completed including Phase Frequency Detector (PFD), Charge Pump,Low Pass Filter (LPF), Voltage Controlled Oscillator (VCO) and Divider. Thirdly, thecharge pump PLL system consisted by these blocks is simulated under differentprocess, temperature and power voltage. From the simulation results, each block andthe whole PLL system have obtained the design specifications. Finally, layout andverification of the PLL circuit are completed and the PLL circuit has been taped out.On the other hand, in the paper VCO and PLL system's phase noise theory andcharacteristic have been deeply researched. VCO's phase noise is predicted byHajimiri's phase noise model and compared with the simulation result. Furthermore,phase noise of the PLL system is simulated and analyzed by PSS (Periodic SmallSignal) method.The achievement of this paper will provide lots of useful guides and referenceson the design of system and module level in PLL circuit, especially on the analysisand simulation of phase noise.