Research And Design On 20MS/s 12bits Successive Approximation Register Analog-to-Digital Converters

In recent years,the size of the semiconductor process has been gradually reduced,so the chip can reduce power consumption and area while increasing speed,and the digital circuits have also benefited from the rapid development of process.Analog-to-Digital Converter(ADC)has the function of converting analog electrical signals into digital electrical signals.It has always been one of the research hotspots of scholars and enterprises,which is widely used in civilian,military and industrial sensors.The high precision,high speed,and energy efficient structure is a huge challenge for ADC circuit designers.The successive approximation register analog-to-digital converter(SAR ADC)has become a popular architecture to achieve high energy efficiency and is widely used in real life.Therefore,this article designed a successive sampling rate of 20 MSps with an accuracy of12 bits.Approximate analog-to-digital converter.This paper shows the performance comparison between this design and traditional SAR ADC under MATLAB modeling,and the design and verification methods of the whole and each part of this module are introduced in detail.In this design,a segmenting capacitor array based on the principle of charge redistribution is adopted.The effective precision of the two segments is 7bits and 5bits respectively,and it is realized through bridge capacitor connection.This design uses a variety of redundancy methods,including sub-radix2 technology and adding compensation capacitors,and the value of the bridge capacitor also ensures redundancy.In the first segment of the DAC,related reverse switching technology(CRS)is used to try to reuse the prior capacitor in the process of successive approximation.This reverses the error caused by the prior capacitor and mitigate the effect of static DAC nonlinearity caused by capacitor mismatch,thereby improving the linearity of the SAR ADC.These mechanisms provide a better balance between speed and resolution,and pave the way for higher sampling rates and better power efficiency.Settling time,logic delay and comparator delay are the key factors which restrict the speed of ADC.In order to solve this problem,this design adopts asynchronous control logic,while reasonably designs the structure and size of capacitor array,digital circuit and comparator.The overall area of the SAR ADC designed in this paper is 230?m×140?m,and the power supply voltage of each module is 1.8V.When the sampling frequency is 20 MSps and the input signal is close to the Nyquist frequency,the previous-circuit simulation results show ENOB is11.40 bits,and the SNDR and SFDR are 70.4d B and 80.4d B,respectively.The post-circuit simulation results show that ENOB is 10.86 bits,and the SNDR and SFDR are 67.1d B and 69.8d B respectively.The overall power consumption of the SAR ADC is 688.52?W,and FOM is26.24 f J/conv-step.The design and simulation of this circuit have been completed in 0.18 ?m process.