Research On Successive Approximation Analog-to-digital Converter Based On Passive Noise Shaping Technology

As the interface between analog signal and digital signal,the Analog-to-digital converters(ADCs)play an irreplaceable role in signal transmission and processing.With the rapid rise of application fields such as Io T technology,portable devices,and wearable medical electronics,ADCs are also developing in the direction of smaller area,higher accuracy,and lower power consumption.At the same time,the intrinsic gain of MOSFET becomes smaller and smaller duo to the continuous development of CMOS technology.It is more difficult to design high-gain operational transconductance amplifiers.Therefore,the traditional ADCs based on operational amplifiers lose their inherent advantages.The Successive Approximation Register(SAR)ADCs have the advantages of simple structure,low power consumption,high digitization,and friendly to the evolution of CMOS process,and can achieve high energy efficiency under advanced processes.However,due to the limitation of comparator noise,it is difficult for SAR ADCs to achieve higher conversion accuracy.Because of utilizing noise-shaping and oversampling technology,which can effectively improve the conversion accuracy,the ?-? ADC is the first choice for highprecision applications.However,the input signal bandwidth is limited as the result of the high oversampling ratio.Furthermore,the power-hungry OTA is mostly used in the ?-?ADC,which is not suitable for low-power applications.The noise-shaping SAR ADC retains the advantages of SAR ADCs,such us low power consumption,small area and low design complexity.At the same time,it combines the over-sampling and noise-shaping technology in the ?-? ADC to achieve higher conversion precision with low oversampling ratio.In recent years,the noise-shaping SAR ADC has become a research hotspot in academia.First of all,the thesis separately elaborates the working principles of traditional SAR ADC and noise-shaping SAR ADC,which laid a theoretical foundation for the design of the following articles.After analyzing the structure of several passive noise shaping SAR ADCs in detail,a second-order fully-passive noise-shaping SAR ADC with CIFF structure is proposed in this thesis.It uses the integration capacitor multiplexing technology to realize the passive addition function by splitting and stacking the integration capacitor.It only uses the two-input pair comparator with an active gain of 1:5 achieving second-order noise shaping.In addition,it obtains two zeros at z=0.8,and the in-band noise suppression is 28 d B.Secondly,the noise introduced in the conversion process of the second-order FPNS SAR ADC is analyzed in detail.The behavioral modeling of the ADC is completed in MATLAB,and the output spectrum is obtained by simulation.Finally,the circuit design of each module is completed.To increase the conversion rate,the asynchronous sequential logic is used in the FPNS SAR.Moreover,the substrate bias elimination technology is adopted in this circuit to reduce the nonlinearity of the sampling switch.The proposed 2nd-order FPNS SAR ADC is implemented in the TSMC 65 nm CMOS process.The simulation results in Cadence show that at 1.2V power supply voltage,40 MS/s sampling rate,-1d BFs@1.25 MHz input sine wave,and oversampling rate of 4,it achieves SNDR of 75.7 d B,the effective number of bits of 12.3 bit,and the signal bandwidth of 5MHz.The overall power consumption of the circuit is 5.84 m W,of which the power consumption of the ADC core is 340 ?W,and the power consumption of the Bandgap reference and the input buffer is 5.5 m W.The calculated Schreier Fo M is 177.4 dB.