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Design Of A 12-bit 200kS/s Energy-Efficient Successive Approximation Register Analog-to-Digital Converter

Posted on:2018-03-20Degree:MasterType:Thesis
Country:ChinaCandidate:X C ZhouFull Text:PDF
GTID:2348330536479894Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
As the interface between analog signal and digital signal,analog-to-digital converter(ADC)is an integral part of modern electronic systems.Compared with other types of ADCs,successive approximation register analog-to-digital converter(SAR ADC)has the characteristics of simple structure and low power dissipation and its performance is not affected by the scaling down of CMOS devices' feature size.Therefore,design of high performance SAR ADC has always been a hot research topic in the field of industry and academia.The successive approximation method causes the internal circuits of SAR ADC working at times of sampling frequency,which means the reference voltage source requires a strong drive capability.However,if the reference voltage is driven by an external circuit,large numbers of decoupling capacitors should be added to suppress vibration.In this dissertation,a 12-bit 200kS/s SAR ADC with integrated reference voltage buffer is designed.To reduce the bandwidth requirement of the reference voltage buffer,the digital-to-analog converter(DAC)begins the settling of the subsequent comparison voltage immediately after the comparator results come out.The SAR logic is also optimized,resulting in semi-synchronous characteristics.In addition,based on the analysis of various types of charge redistribution DACs,a RC hybrid DAC which utilizes the output resistor of the reference voltage buffer is proposed to improve the integration.The behavioral modeling and simulation verification are carried out in Matlab software.The design of the chip is implemented in CSMC 0.18?m CMOS process.The total chip area is 1.3×1.1mm2 and the core area is 540×370?m2.The analog and digital parts are powered by 3.3V and 1.8V respectively.The post-simulation results show that the proposed SAR ADC has a DNL of-0.1/0.6LSB and an INL of-0.9/0.5LSB.When the reference voltage is 2V and a 99.4kHz sinusoidal input is applied,simulation shows 11.05-bit ENOB,76.5dB SFDR and 245?W power consumption.
Keywords/Search Tags:successive approximation register, analog to digital converter, reference buffer, comparator
PDF Full Text Request
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