Design For A Successive Approximation Register Analog-to-digital Converter Based On CMOS Technology

Digital circuit occupies an important position in the field of integrated circuits because of its rapid development and advantage of high efficiency and low cost.In reality,most signals are unprocessed and analogic,so the analog-to-digital converter is significant device which can turn analog signal into digital signal.It is also a matter of great concern.Successive approximation register analog-to-digital converter(SAR ADC)has the advantage of simple circuit structure,small area and few analog circuits.It can be compatible with fast developing CMOS technology and has been widely used in low power embedded system and portable equipment.A 1MS/s,8-bit SAR ADC is designed in this thesis.In digital-to-analog converter(DAC),a single-ended structure is applied to reduce the number of switches and power consumption.In addition,a dummy capacitor array is used to compensate for clock feedthrough and comparator offset voltage.The proposed dynamic comparator with preamplifier stage is designed,which can effectively isolate the input to output while adjusting input offset voltage.An improved Bit-Slice unit module is used in digital timing to implement SAR logic.It not only reduces the number of MOS tube,but also achieves low power performance.For 1MS/s sampling rate,the ADC dissipating 16.5μW from a 1.8V supply,achieves a FOM of 65.8fJ/step for a 5.86-KHz input.It achieves SNR and SNDR of 50.1dB and 49.3dB,and it also achieves SFDR and ENOB of 68.6dB and 7.89 bit respectively.Finally,a low power SAR ADC based on signal auto-correlation is proposed.By sampling and converting only difference between two successive input samples,it carries out analog to digit conversion with fewer bits if the difference is smaller than a certain threshold,which can reduce power consumption.At the end,lots of simulations are carried out to verify them.