Font Size: a A A

A Study Of Analog-to-Digital Converter Based On Sigma-Delta Noise-shaping Scheme

Posted on:2019-10-19Degree:MasterType:Thesis
Country:ChinaCandidate:Y DongFull Text:PDF
GTID:2428330572458995Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Due to its high-power efficiency in nanometer technology,successive approximation register analog-to-digital converter?SAR ADC?is of great popularity for medium-resolution applications.However,as the target resolution goes beyond 10-bit,its efficiency quickly diminishes due to its tight requirement on comparator noise.The exponentially increasing capacitor DAC array costs more area and power,which makes it difficult to drive.For high-resolution application,Sigma-Delta ADC is a more widely-used architecture,but its valid bandwidth is limited for the high oversampling radio.Taking advantage of both noise shaping feature of Sigma-Delta modulator and high-power efficiency of SAR ADC,noise-shaping SAR ADC is an emerging architecture for solving the tradeoff between resolution and bandwidth.This thesis presents a fully-passive noise-shaping?FPNS?successive approximation register analog-to-digital converter?SAR ADC?.In order to improve the performance for higher precision,an additional 1st order noise shaping is realized by a fully-passive technique in the quantizer.It is fully passive and only needs minor modification to a conventional SAR ADC.Through a passive integrator,quantization noise,comparator noise and DAC noise are shaped with a noise transfer function of(1-0.8z-1).It still inherits the merits of a SAR ADC which is robust to low voltage operation and technology scaling.Unlike conventional multi-bit Sigma-Delta ADCs,both the noise transfer function and the error transfer function of DAC mismatches are immune to process-voltage-temperature variations.The circuit is simulated in SMIC 0.18?m CMOS process,and adopts the 8-bit split re-used DAC capacitor array scheme.The modulator achieves a 68.9dB SNDR and an ENOB of11.16 bit with a signal bandwidth of 62.5 KHz and a sampling clock of 1 MS/s.It consumes 12.0?W from a 1.0 V power supply.The ADC core occupies an active area of350×400?m2.The calculated Schreier Figure of Merit?FoM?and Walden FoM are 166dB and 42 fJ per conversion step,respectively.The noise-shaping is realized with an improvement of 3-bit above the 8-bit DAC capacitor array and the low frequency noise is greatly suppressed.
Keywords/Search Tags:fully-passive noise-shaping, successive-approximation register, oversample, analog-to-digital converter, 0.18?m CMOS
PDF Full Text Request
Related items