Design And Implementation Of Fractional Frequency Phase-Locked Loop In Radio Frequency Transceiver

In modern communication systems based on wireless technology,radio frequency transceivers are a crucial part.Its characteristic is that it can transmit and receive signals without cables,and its performance determines the quality of wireless communication.As one of the core modules in rf transceiver,phase locked loop is mainly used for generating the reference clock signal of the front end and back end circuits of the transceiver.The stability of the signal source it provides determines the quality of the signal after frequency conversion,and its performance determines the performance of the whole transceiver.The minimum resolution of the frequency point determines the width of the channel,and the switching speed of the frequency point determines the response speed of the transceiver.Due to the high working frequency and complex working mode,the phase locked loop technology is still a hot topic in the extremely developed wireless communication technology.The phase locked loop of fractional frequency division mainly realizes fractional frequency division by frequently switching frequency division ratio of the divider,and then introduces problems such as fractional stray and quantization noise.This paper analyzes the non-ideal factors of each module of PLL and improves the performance of each module,so as to improve the phase noise performance of PLL,reduce the power consumption,reduce the locking time of PLL and other reference indexes.at the same time,?-? modulator based on MASH 1-1-1 structure output signal quantization noise into the high frequency,thus reduce the decimal frequency divider is introduced into the traditional decimal stray.Based on this design idea,a phase locked loop circuit with fractional frequency division which can be used in radio frequency transceiver is designed in 0.18?m CMOS process.Its main contents are as follows:This paper analyzes the realization principle of the phase locked loop with fractional frequency division and the parameter indexes that affect its performance,gives the linear model and phase noise model of the phase locked loop,and completes the design and simulation according to the index sub-module of the design plan.An fractional frequency Phase-locked loop with input frequency of 14MHz and a frequency resolution of 26.68Hz were completed.In the design process,the PFD adds the reset delay signal EN to avoid the "dead zone effect" of phase discrimination.A dynamically matched charge pump circuit based on negative feedback is designed,so that it still has low power loss distribution in a wide range of output voltage.The simulation results show that when the power supply voltage is 1.8V,the output current of the charge pump is 10?A,and when the output voltage varies within the range of 0.2-1.5V,the maximum electric loss distribution is only 0.12%.In the tail current design of VCO,the numerical control tuning resistance array is used to replace the traditional MOS tube tail current.With the cooperation of amplitude tuning mechanism,not only a low power consumption and low noise VCO with tuning range of 1.4GHz to 2.1GHz and tuning ratio of 48.6%is realized.Compared with traditional MOS tail current LC-VCO at the same power consumption,the effectiveness of digital tunable resistance array is verified.Compared with the listed references,it has better phase noise performance and performance index.Under the typical PVT corner,when the carrier frequency is 1.85GHz,the phase noise is-127.2dBc/Hz@1MHz,and the consumption current is 496?A under the 1.8V supply voltage.The FoM and the FoMT are-193.06dBc/Hz and-206.7dBc/Hz,respectively.Finally,completed the ?-?Fractional divider based on MASH1-1-1 structure,the quantization noise to high frequency,the loop filter and use the system to filter out the noise,solves the decimal frequency divider is introduced into decimal stray.Simulation of the system shows that when the VCO output frequency is 1.75GHz and the system output signal is stable,the locking time is 31?s,the control voltage is 673mV,and the phase noise is-112dBc/MHz@1MHz.