Design Of Quick Lock Non-Oscillator Phase Locked Loop

The Phase-Locked Loop (PLL) is synchronizing circuit which can make the input reference signal exactly consist with the output signal in phase and frequency. With the rapid development of electronic technology, the integrated CMOS PLL has been a large number of applications. The shadow of the CMOS PLL can be seen everywhere from the consumption of electronics to the instrumentations, from the microprocessors to the large-scale mobile communication devices. Due to the extensive application of the PLL, the PLL has been the focus of academic research.A variety of PLL are appeared, like the linear analog PPL, the high-performance mixed digital-analog PPL and the digital PPL. In many PPL structures, the mixed digital-analog PPL has been widely used in practical applications, because of its low jitter, low power consumption, no phase difference, large capture range and ease integration. Cost pressures forced humans to design the chip, which are integrated into more and more independent external components in integrated circuit design. So the product costs could be reduced while greatly improved the reliability of the product.In this context, The Non-oscillator PLL was designed, that is the precision charge pump PLL of non-oscillator, including the reference oscillator, the voltage controlled oscillator (VCO), the charge pump (CP), the low-pass filter (LPF), the phase frequency detector (PFD) and digital tracking divider. The analog module similarity with classical architecture, the digital tracking divider module has its own unique features:the use of the initial PLL inaccurate clock search system synchronization signal, obtaining the reference clock and a corresponding adjustment to the output of the PLL, so that only one host reference signal can pinpoint the desired clock frequency.In this paper, a0.18μm CMOS process were applied, the digital circuits modules and the analog circuits modules were used Spectre and ModelSim software to simulate and verify separately, and then emulate the whole system. When the external system reference clock were used a low-frequency clock (0.5KHz), the PPL system were achieved a steady state after a reference (about300μs). But the ordinary analog PPL requires a number of reference clock cycles in this environment, it will take a few milliseconds to tens of milliseconds to complete lock. The mixed analog-digital PPL achieved a fast locking of PPL, improved the application convenience while also improved the reliability of the circuit to achieve the desired results.